 |
Ashok Srivastava
Professor |
Research Interests:
Low Power VLSI Circuit
Design and Testability (Digital, Analog and Mixed-Signal); Noise in
Devices and Integrated Circuits;
Nanoelectronics (Quantum
Electronic Devices, Graphene Electronics,
Carbon Nanotube (CNT)
Interconnects, CNT-FETs and Integrated Circuits); VLSI Design for
Wireless Communications; RF MEMS/NEMS and Integrated Circuits; Smart
Sensors and CMOS-MEMS/NEMS Micro/Nano systems; Semiconductor Device
Modeling; Radiation-Hardened Integrated Circuits; and
Low-Temperature Electronics.
Biographical Sketch:
Ashok Srivastava received B.Sc., B.Sc. (Hons.) and M.Sc. (Physics)
degrees with specialization in advanced electronics from the
University of Lucknow, India, in 1966, 1967, and 1968, respectively.
He obtained M. Tech. and Ph.D. degrees in Solid State Physics and
Semiconductor Electronics area from the Indian Institute of
Technology, Delhi in 1970 and 1975, respectively. He joined the
Department of Electrical & Computer Engineering at Louisiana State
University, Baton Rouge in 1990 as an Associate Professor and
currently is a Professor. He has previously served as a Scientist at
the Central Electronics Engineering Research Institute, Pilani,
India (1975-84), and was on the faculty of Birla Institute of
Technology and Science, Pilani, India (1975); North Carolina State
University, Raleigh (1985-86); State University of New York, New
Paltz (1986-90); University of Cincinnati, Cincinnati and as a
UNESCO Fellow (1979); as a Visiting Scientist and UNESCO Fellow at
the University of Arizona, Tucson (1979-80). During summer 1996 he
was the AFOSR Faculty Fellow at the Kirtland Air Force Base, New
Mexico and in summer 2004 he was the NASA Faculty Fellow at the Jet
Propulsion Laboratory/California Institute of Technology, Pasadena.
He is the author of more than 130 technical papers, including
conference proceedings and a book chapter. He has graduated 37
students who are employed by academic institutions, VLSI chip design
and semiconductor companies. He has many professional presentations
including invited talks. He is reviewer of several international
journal papers and books and has served on national review panels
and program committees of many international conferences. He has
been awarded many grants and contracts from federal, state, industry
and foundations. He is a senior member of IEEE, Electron Devices,
Circuits and Systems, and Solid-State Circuits Societies, and member
of SPIE and ASEE.
Current PhD Students:
Yao Xue (yxu7@tigers.lsu.edu)
Yang Liu (yliu11@tigers.lsu.edu)
Rajiv Soundararajan (rsound1@tigers.lsu.edu)
Juyu Wang (jwang47@tigers.lsu.edu)
Summer Intern (2010):
Spandana Lekkala , Indian Institute of Technology, Patna
(slekkala@tigers.lsu.edu)
Graduated PhD Students:
Jose M. Marulanda (Summer 2008)
Chi Zhang (Fall 2006)
Chuang Zhang (Spring 2005)
Recent Graduated MS Students:
Hemalatha Mekala (Fall 2009)
Josephine Sathiaraj (Fall 2009)
Undergraduate Courses:
EE 4242: VLSI Design; EE 4240: Linear Circuit Design; EE 4250:
Digital Integrated Circuit
Graduate Courses:
EE 7242: VLSI Systems; EE 7248: Mixed-Signal Integrated Circuit
Design; EE 7246: Integrated Sensors and Actuators; EE 7000: Wireless
Communications: System Design and (VLSI) Circuit Implementation; and
EE7200: Nanoelectronics (future)
Journal Publications (2005 - present):
A. Srivastava, Y. Xu and A. K. Sharma, “Carbon nanotubes for next
generation very large scale integration
interconnects,” J.
Nanophotonics, (invited paper), vol. 4, 041690, pp.1-26, 17 May
2010 (online).
Y. Xu, A. Srivastava and A.K. Sharma, "Emerging carbon nanotube
electronic circuits, modeling and performance," VLSI Design (invited
paper), vol. 2010, Article ID 864165, pp. 1-8, 2010.
DOI: 10.1155/2010/864165 (online).
A. Srivastava, S. Yellampalli, P. K. Alli and S. S. Rajput,
“Combined oscillation and IDDQ testing of a CMOS
amplifier circuit,” Int. J.
of Electronics, vol. 97, Issue 1, pp. 1-15, January 2010.
A. Srivastava, J. Marulanda, Y. Xu and A. K. Sharma, “Current
transport modeling of carbon nanotube field effect transistors,”
physica status solidi (a),
vol. 206, no. 7, pp. 1569-1578, 2009.
Y. Xu and A. Srivastava, “A model for carbon nanotube
interconnects,” Int. J. of
Circuit Theory and Applications,
published online in Wiley InterScience, DOI: 10.1002/cta.587, pp.
1-17, 2009.
S. S. Yellampalli and A. Srivastava, “DIDDQ
testing of CMOS Data Converters,”
J. Active & Passive Devices,
vol. 4, pp. 63-89, 2009.
A. Srivastava and C. Zhang, “An adaptive body-bias generator for low
voltage CMOS VLSI circuits,”
Int. J. Distributed Sensor Networks, vol. 4, issue 2, pp.
213-222, May 2008 (Special Issue: Advances on Heterogeneous Wireless
Sensor Networks).
J. M. Marulanda, A. Srivastava and A.K. Sharma, “Threshold and
saturation voltages modeling of carbon nanotube field effect
transistors (CNT-FETs),” NANO,
vol. 3, no. 3, pp. 195-201, 2008.
J. M. Marulanda and A. Srivastava, “Carrier density and effective
mass calculations in carbon nanotubes,
physica status solidi
(b), vol. 245, no. 11, pp. 2558-2562, 2008.
S. S. Yellampalli and A. Srivastava, “DIDDQ
based testing of submicron CMOS based digital-to-analog converter
circuits,” J. Active &
Passive Devices, vol. 3, pp. 341-353, 2008.
S. R. Herlekar, H.-C. Wu, M. Saquib and A. Srivastava, "Hot carrier
effects in wireless communication systems built on short-channel
MOSFETs," IEEE Trans. on
Wireless Communications (Letters), vol. 6, no. 7, pp. 2402-2406,
2007.
Chi Zhang and A. Srivastava, “Hot carrier effects on jitter
performance in CMOS voltage-controlled oscillators,”
Fluctuation and Noise Letters,
vol. 6, no. 3, pp. L329-L334, 2006.
C. Zhang, A. Srivastava and P. K. Ajmera, “A 0.8 V CMOS amplifier
design,” J. Analog Integrated
Circuits and Signal Processing, vol. 47, pp. 315-321, 2006.
S. R. Herlekar, H.-C. Wu, Chi Zhang and A. Srivastava,
“OFDM performance analysis in the phase noise arising from the
hot-carrier effect,” IEEE
Trans on Consumer Electronics, vol. 52, no. 3, pp. 757-765, Aug.
2006.
M. Feldman, A. El-Amawy, A. Srivastava and R. Vaidyanathan,
“Adjustable Wallaston-like prisms,”
Review of Scientific
Instruments, vol. 77, pp. 066109-1 to 2, 2006.
A. Srivastava, S. Aluri and A. K. Chamakura, “A simple built-in
current sensor for IDDQ testing of CMOS data converters,”
Integration, the VLSI Journal, vol. 38/4, pp. 579-596, 2005.
Conference Publications (2005 - present):
R. Soundararajan, A. Srivastava and S. Yellampalli, “Process
variation effects on delta-IDDQ testing of CMOS data
converters,” 53rd
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS
10), (Seattle, Washington, August 1-4, 2010)
Y. Xu, A. Srivastava and S. Rai, “Fault modeling in carbon nanotube
based digital integrated circuits,” in
The 2010 ASEE Gulf Southwest
Annual Conference, (Lake Charles, LA, March 24-26, 2010).
R. Soundararajan and A. Srivastava, “Hot carrier stress effect on
the performance of second order oversampling CMOS delta-sigma
modulator,” in The 2010 ASEE
Gulf Southwest Annual Conference, (Lake Charles, LA, March
24-26, 2010).
Y. Liu and A. Srivastava, “Effect of hot carrier injection and
negative bias temperature instability on the performance of CMOS
phase-locked loops,” in The
2010 ASEE Gulf Southwest Annual Conference, (Lake Charles, LA,
March 24-26, 2010).
Y. Liu and A. Srivastava, “Hot carrier effects on CMOS phase-locked
loop frequency synthesizers,” in
11th International
Symposium on Quality Electronic Design (ISQUED), (San Jose, CA,
March 22-24, 2010).
Y. Liu and A. Srivastava, “Reliability considerations in switchable
PLL frequency synthesizers for wireless sensor netwoks,” in
Proc.
SPIE Conference 7646: Nano-,
Bio-, and Info-Tech Sensors and Systems, vol. 7646, (San Diego,
March 7-11, 2010).
R. Soundararajan and A. Srivastava, “A programmable second order
oversampling CMOS sigma-delta analog-to-digital converter for
low-power sensor interface electronics,” in
Proc.
SPIE Conference 7646: Nano-,
Bio-, and Info-Tech Sensors and Systems, vol. 7646, (San Diego,
March 7-11, 2010).
R. Soundararajan, A. Srivastava and J. Kamar, “A programmable second
order oversampling CMOS sigma-delta analog-to-digital converter for
wireless sensor networks,”
Proc. of the 12th International Conference on Information
Technology (ICIT 2009), pp. 227-232, (Bhubaneswar, India,
December 21-24, 2009).
Y. Xu, A. Srivastava, A.K. Sharma and R.K. Nahar, “Circuit modeling
and performance analysis of carbon nanotube interconnects,” in
Proc. of 15th
International Workshop on the Physics of Semiconductor Devices,
(Delhi, India, December 15-19, 2009).
Y. Xu and A. Srivastava, “Dynamic response of carbon nanotube field
effect transistor circuits,”
Proc. 2009 NSTI
Nanotechnology Conference and Expo, vol. 1, pp. 625-628,
(Houston, TX, May 3-7, 2009).
Y. Xu and A. Srivastava, “A model of multi-walled carbon nanotube
interconnects,” in 52nd
IEEE Midwest Symposium on Circuits and Systems, (Cancun, Mexico,
August 2-5, 2009). This
paper was one of the 12 finalists in 290 submitted papers for the
Student Paper Competition (SPC).
Y. Xu and A. Srivastava, “Transient behavior of integrated carbon
nanotube field effect transistor circuits and bio-sensing
applications,” Proc.
SPIE Conference 7291: Nano-,
Bio-, and Info-Tech Sensors and Systems, vol. 7291, pp. 729101-1
to 729101-11 (San Diego, March 9-11, 2009).
Y. Liu, A. Srivastava and Y. Xu, “A switchable PLL frequency
synthesizer and hot carrier effects,”
Proc. IEEE/ACM
19th Great Lakes
Symposium on VLSI Systems (GSLVLSI 2009), pp. 481-486 (Boston,
MA, May 10-12, 2009).
Y. Xu, A. Srivastava and J.M. Marulanda, “Emerging carbon nanotube
electronic circuits, modeling and performance,”
Proc. of
51st IEEE
International Midwest Symposium on Circuits and Systems (MWSCAS08),
pp. 566-569 (Knoxville, TN, August 10-13, 2008).
J. M. Marulanda, A. Srivastava and S. Yellampalli, “Numerical
modeling of the I-V characteristics of the carbon nanotube field
effect transistors,” Proc.
IEEE 40th
Southeastern Symposium on System Theory (SSST 2008), pp.
235-238, (New Orleans, LA, March 16-18, 2008).
J. M. Marulanda, A. Srivastava and A.K. Sharma, “Current transport
modeling in carbon nanotube field effect transistors (CNT-FETs) and
bio-sensing applications,”
Proc. SPIE Nano- and
Micro-Sensors for Bio-Systems (SSNO6), vol. 6931, pp. 693108-1
to 693108-9 (San Diego, CA, March 9-13, 2008).
J. M. Marulanda, A. Srivastava and A.K. Sharma, “Transfer
characteristics and high frequency modeling of logic gates using
carbon nanotube field effect transistors (CNT-FETs),”
Proc. 20th Symp.
on Integrated Circuits and Systems Design (SBCCI2007), pp.
202-206, (Rio de Janeiro, Brazil, September 3 to 6, 2007).
J. M. Marulanda and A. Srivastava, “Carrier density and effective
mass calculations for carbon nanotubes,”
Proc.
2007 IEEE
International Conference on
Integrated Circuit Design and Technology, pp. 234-237 (Austin,
Texas, May 30th – June 1st, 2007).
Y. Xu and A. Srivastava, “A two-port network model of CNT-FET for RF
characterization,” Proc.
50th IEEE
International Midwest Symposium on Circuits and Systems,
(Montreal, Canada, August 5-8, 2007).
Y. Xu and A. Srivastava, “New energy recovery CMOS/XOR gates,”
Proc.
50th IEEE
International Midwest Symposium on Circuits and Systems,
(Montreal, Canada, August 5-8, 2007).
S. Yellampalli and A. Srivastava, “A BICS for
DIDDQ
testing of a 12-bit recycling architecture based ADC,”
2007 IEEE Region 5 Technical
Professional, and Student Conference, (University of Arkansas,
Fayetteville, April 20-22, 2007).
Chi Zhang, A. Srivastava, C. Ni, "An experimental study of phase
noise in CMOS phase-locked loops considering different noise
sources,” Proc.
49th IEEE
International Midwest Symposium on Circuits and Systems, (San
Juan, Puerto Rico, August 6-9, 2006).
This paper was one of the 12 finalists in 144 submitted papers from
27 countries for the Student Paper Competition (SPC).
A. Srivastava, S. Yellampalli and K. Golla, “Delta-IDDQ
testing of a CMOS 12-bit charge scaling digital-to-analog
converter,” Proc.
49th IEEE
International Midwest Symposium on Circuits and Systems, (San
Juan, Puerto Rico, August 6-9, 2006).
A. Srivastava, R. Soundararajan and J.-C. Hsu, “CMOS chip chemical
detection system comprising mass-sensitive nanocantilevers,”
Proc. SPIE, vol. 6172,
pp. 617200Y-1 to 61720Y-10, 2006 (San Diego, CA, Feb. 26 - March 2,
2006).
S.R. Herlekar, H.-C. Wu, Chi Zhang and A. Srivastava,
“OFDM performance analysis in the presence of synchronization errors
induced by hot carriers,”
Proc. IEEE 62nd Semiannual Vehicular Technology
Conference (VTC), vol. 3, pp. 1844-1848, 2005 (Dallas, TX, Sept.
25-28, 2005).
J. M. Marulanda, A. Srivastava and R.K. Nahar, “Ultra-high frequency
modeling of carbon nanotube field-effect transistors (CNT-FETs),
Proc 13th International Workshop on the Physics of
Semiconductor Devices (IWPSD), Dec. 13-17, 2005, Delhi.
J. M. Marulanda and A. Srivastava, “I-V characteristics modeling and
parameter extraction for CN-FETs,”
Proc.
2005 International
Semiconductor Device Research Symposium, Dec. 7-9, 2005,
Bethesda MD.
Chi Zhang, A. Srivastava and H.-C. Wu, “Hot-electron induced effects
on noise and jitter in submicron CMOS phase-locked loop circuits,”
Proc.
48th IEEE
International Midwest Symposium on Circuits and Systems, pp.
507-510, (Cincinnati, OH, August 7-10, 2005).
S. Yellampalli, A. Srivastava and V.K. Pulendra, “A combined
oscillation, power supply current, and IDDQ testing
methodology for fault detection in floating gate input CMOS
operational amplifier,” Proc.
48th IEEE
International Midwest Symposium on Circuits and Systems, pp.
503-506, (Cincinnati, OH, August 7-10, 2005).
A. Srivastava and R.R. Anantha, “A programmable oversampling
sigma-delta analog-to-digital converter,”
Proc.
48th IEEE
International Midwest Symposium on Circuits and Systems, pp.
539-542, (Cincinnati, OH, August 7-10, 2005), 2005.
S. R. Herlekar, H.C. Wu, Chi Zhang and A. Srivastava, “Suppression
of phase noise in OFDM synchronization devices using ICI
self-cancellation coding,”
Proc. IEEE Global
Telecommunications Conference (GLOBECOM), vol. 1, pp. 230-234,
2005, (St. Louis, MO, Nov. 28 - Dec. 2,
2005).
Chi Zhang and A. Srivastava, “Hot carrier effects on jitter and
phase noise in CMOS voltage-controlled oscillators,”
Proc. of SPIE - Noise in
Devices and Circuits III, vol. 5844, pp. 52-62, 2005, (Austin,
TX, May 23-26, 2005).
A. Srivastava, S. S. Yellampalli and V. Pulendra, “A combined noise
analysis and power supply current based testing of CMOS analog
integrated circuits,” Proc.
of SPIE - Noise in Devices and Circuits III, vol. 5844, pp.
230-237, 2005, (Austin, TX, May 23-26, 2005).
S. S. Yellampalli and A. Srivastava, “A simple noise modeling based
testing of CMOS analog integrated circuits,”
Proc. of SPIE - Noise in Devices and Circuits III, vol. 5844,
pp. 276-283, 2005, (Austin, TX, May 23-26, 2005).
S. R. Herlekar, Chi Zhang, H. Wu and A. Srivastava, “Phase noise
analysis for OFDM
systems based on hot-carrier effects in synchronization
electronics,” Proc. of SPIE -
Noise in Communication Systems, vol. 5847, pp. 150-159, 2005,
(Austin, TX, May 23-26, 2005).
T. Xin, P. K. Ajmera, C. Zhang and A. Srivastava, “Post-CMOS
chip-level processing for high-aspect ratio microprobe fabrication
utilizing pulse plating,”
Proc. of SPIE – Smart Electronics, MEMS, BioMEMS, and Nanotechnology,
vol. 5763, pp. 1-10, 2005, (San Diego, CA, March 6-10, 2005).
V. R. Gaddam, J. Yernagula, R. R. Anantha, S. Kona, S. Kopparthi, P.
K. Ajmera and A. Srivastava, “Remote power delivery for hybrid
integrated bio-implantable electrical stimulation system,”
Proc. of SPIE – Smart
Electronics, MEMS, BioMEMS, and Nanotechnology, vol. 5763, pp.
20-31, 2005, (San Diego, CA, March 6-10, 2005).