Ashok Srivastava       Professor Address:       Louisiana State University       Dept. of Elect. & Computer Eng.       Baton Rouge, LA 70803-5901 Tel:      225-578-5622 Fax:     225-578-5200 E-mail:  ashok@ece.lsu.edu

Research Interests:

Low Power VLSI Circuit Design and Testability (Digital, Analog and Mixed-Signal); Nanoelectronics (Quantum Electronic Devices, Carbon Nanotube (CNT) Interconnects, CNT-FETs and Integrated Circuits); VLSI Design for Wireless Communications; RF MEMS/NEMS and Integrated Circuits; Smart Sensors and CMOS-MEMS/NEMS Micro/Nano systems; Semiconductor Device Modeling; Radiation-Hardened Integrated Circuits; and Low-Temperature Electronics.

Biographical Sketch:

Ashok Srivastava received B.Sc., B.Sc. (Hons.) and M.Sc. (Physics) degrees with specialization in advanced electronics from Lucknow University, India, in 1968, 1969, and 1970, respectively. He obtained his M. Tech. and Ph.D. degrees in Solid State Physics and Semiconductor Electronics area from Indian Institute of Technology, Delhi, India in 1970 and 1975, respectively. He joined the Electrical & Computer Engineering Department at Louisiana State University in Baton Rouge in 1990 as an Associate Professor and currently is a Professor. He has previously served as a Scientist at the Central Electronics Engineering Research Institute, Pilani, India (1975-84), and was on the faculty of Birla Institute of Technology and Science, Pilani, India (1975); North Carolina State University, Raleigh (1985-86); State University of New York, New Paltz (1986-90); University of Cincinnati, Cincinnati and as a UNESCO Fellow (1979); as a Visiting Scientist and UNESCO Fellow at the University of Arizona, Tucson (1979-80). During summer 1996 he was the AFOSR Faculty Fellow at Kirtland Air Force Base, New Mexico and in summer 2004 he was the NASA Faculty Fellow at Jet Propulsion Laboratory/California Institute of Technology, Pasadena. He is the author of more than 100 technical papers, including conference proceedings and a book chapter. He has graduated 33 students who are employed by VLSI chip design and semiconductor companies. He has many professional presentations including invited talks. He is reviewer of several international journal papers and books and has served on national review panels and program committees of several international conferences. He has been awarded many grants and contracts from federal, state, industry and foundations. He is a senior member of IEEE, Electron Devices, Circuits and Systems, and Solid-State Circuits Societies, and member of SPIE and ASEE.

Graduated PhD Students:

Chuang Zhang (Spring 2005)
Chi Zhang (Fall 2006)
Jose M. Marulanda (Summer 2008)

Current PhD Students:

Siva S. Yellampalli (syella1@lsu.edu)
Yang Liu (yliu11@lsu.edu)
Yao Xue (yxu7@lsu.edu)
Rajiv Soundararajan (rsound1@lsu.edu)
Qiang Yu (qyu2@lsu.edu)

Current MS Students:

Hemalatha Mekala (hmekal1@lsu.edu)
Josephine Sathiaraj (jsathi1@lsu.edu)

Undergraduate Courses: EE 4242: VLSI Design; EE 4240: Linear Circuit Design; EE 4250: Digital Integrated Circuit

Graduate Courses: EE 7242: VLSI Systems; EE 7248: Mixed-Signal Integrated Circuit Design; EE 7246: Integrated Sensors and Actuators; EE 7000: Wireless Communications: System Design and (VLSI) Circuit Implementation; and EE7200: Nanoelectronics (future)

Recent Publications (journals):

J. M. Marulanda, A. Srivastava and A. K. Sharma, "Threshold and saturation voltages modeling of carbon nanotube field effect transistors (CNT-FETs)," NANO, 2008 (in print).

J. M. Marulanda and A. Srivastava, "Current transport modeling of carbon nanotube field effect transistors," physica status solidi (a), 2008 (in print)

S. S. Yellampalli and A. Srivastava, "Delta-IDDQ based testing of submicron CMOS based digital-to-analog converter circuits," J. Active & Passive Devices, accepted 2008 (in print).

S. S. Yellampalli and A. Srivastava, "Delta-IDDQ testing of CMOS Data Converters," J. Active & Passive Devices, accepted 2008 (in print).

A. Srivastava and C. Zhang, "An adaptive body-bias generator for low voltage CMOS VLSI circuits," Int. J. Distributed Sensor Networks, vol. 4, issue 2, pp. 213-222, May 2008 (Special Issue: Advances on Heterogeneous Wireless Sensor Networks).

S. R. Herlekar, H.-C. Wu, M. Saquib and A. Srivastava, "Hot carrier effects in wireless communication systems built on short-channel MOSFETs," IEEE Trans. on Wireless Communications (Letters), vol. 6, no. 7, pp. 2402-2406, 2007.

Chi Zhang and A. Srivastava, “Hot carrier effects on jitter performance in CMOS voltage controlled oscillators,” Fluctuation and Noise Letters, vol. 6, no. 3, pp. L329-L334, 2006.

C. Zhang, A. Srivastava and P.K. Ajmera, “A 0.8 V CMOS amplifier design,” J. Analog Integrated Circuits and Signal Processing, vol. 47, pp. 315-321, 2006.

A. Feldman, A. El-Amawy, A. Srivastava, and R. Vaidyanathan, “Adjustable Wollaston-like prisms,” Rev. of Scientific Instruments, vol. 77, pp. 066109-1 to 2, 2006.

C. Zhang, A. Srivastava and P. K. Ajmera, “A 0.8 V CMOS amplifier design,” J. Analog Integrated Circuits and Signal Processing, vol. 47, pp. 315-321, 2006.

S. R. Herlekar, H.-C. Wu, Chi Zhang and A. Srivastava, “OFDM performance analysis in the phase noise arising from the hot-carrier effect,” IEEE Trans. on Consumer Electronics, vol. 52, no. 3, pp. 757-765, August 2006.

S. R. Herlekar, H.-C. Wu, M. Saquib and A. Srivastava, "Hot carrier effects in wireless communication systems built on short-channel MOSFETs," IEEE Trans. on Wireless Communications (Letters), 2006 (in print).

A. Srivastava, S. Aluri and A. K. Chamakura, “A simple built-in current sensor for IDDQ testing of CMOS data converters,” Integration, the VLSI Journal, vol. 38/4, pp. 579-596, 2005.

C. Zhang, A. Srivastava and P. K. Ajmera, “Noise analysis of a 0.8 V ultra-low power operational amplifier,” Fluctuations and Noise Letters (special issue on Noise in Devices and Circuits), vol. 4, no. 2, pp. L403-L412, June 2004.

C. Zhang, A. Srivastava and P. K. Ajmera, “Low voltage CMOS Schmitt trigger circuits,” Electronics Letters, vol. 39, no. 24, pp. 1696-1698, 27th November 2003.

A. Srivastava and H.N. Venkata, “Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETs,” Integration, the VLSI Journal, vol. 36, issue 3, pp. 87-101, 2003.

Recent Publications (conferences):

Y. Xu, A. Srivastava and J.M. Marulanda, "Emerging carbon nanotube electronic circuits, modeling and performance," 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS08), (Knoxville, TN, August 10-13, 2008).

J. M. Marulanda, A. Srivastava and S. Yellampalli, "Numerical modeling of the I-V characteristics of the carbon nanotube field effect transistors," Proc. IEEE 40th Southeastern Symposium on System Theory (SSST 2008), pp. 235-238, (New Orleans, LA, March 16-18, 2008), accepted 2008.

J. M. Marulanda, A. Srivastava and A.K. Sharma, "Current transport modeling in carbon nanotube field effect transistors (CNT-FETs) and bio-sensing applications," Proc. SPIE Nano- and Micro-Sensors for Bio-Systems (SSNO6), vol. 6931, pp. 693108-1 to 693108-9 (San Diego, CA, March 9-13, 2008).

J. M. Marulanda, A. Srivastava and A.K. Sharma, "Transfer characteristics and high frequency modeling of logic gates using carbon nanotube field effect transistors (CNT-FETs)," Proc. 20th Symp. on Integrated Circuits and Systems Design (SBCCI2007), pp. 202-206, (Rio de Janeiro, Brazil, September 3 to 6, 2007).

J. M. Marulanda and A. Srivastava, "Carrier density and effective mass calculations for carbon nanotubes," Proc. 2007 IEEE International Conference on Integrated Circuit Design and Technology, pp. 234-237 (Austin, Texas, May 30th June 1st, 2007).

Y. Xu and A. Srivastava, "A two-port network model of CNT-FET for RF characterization," Proc. 50th IEEE International Midwest Symposium on Circuits and Systems, (Montreal, Canada, August 5-8, 2007).

Y. Xu and A. Srivastava, "New energy recovery CMOS/XOR gates," Proc. 50th IEEE International Midwest Symposium on Circuits and Systems, (Montreal, Canada, August 5-8, 2007).

S. Yellampalli and A. Srivastava, "A BICS for Delta-IDDQ testing of a 12-bit recycling architecture based ADC," 2007 IEEE Region 5 Technical Professional, and Student Conference, (University of Arkansas, Fayetteville, April 20-22, 2007).

Chi Zhang, A. Srivastava, C. Ni, "An experimental study of phase noise in CMOS phase-locked loops considering different noise sources,” Proc. 49th IEEE International Midwest Symposium on Circuits and Systems, (San Juan, Puerto Rico, August 6-9, 2006). This paper was among the 12 finalists in 144 papers from 27 countries for the Student Paper Competition (SPC).

A. Srivastava, S. Yellampalli and K. Golla, “Delta-IDDQ testing of a CMOS 12-bit charge scaling digital-to-analog converter,” Proc. 49th IEEE International Midwest Symposium on Circuits and Systems, (San Juan, Puerto Rico, August 6-9, 2006).

A. Srivastava, R. Soundararajan and J.-C. Hsu, “CMOS chip chemical detection system comprising mass-sensitive nanocantilevers,” Proc. SPIE, vol. 6172, pp. 617200Y-1 to 61720Y-10, 2006 (San Diego, CA, Feb. 26 - March 2, 2006).

Chi Zhang, A. Srivastava and H.-C. Wu, “Hot-electron induced effects on noise and jitter in submicron CMOS phase-locked loop circuits,” Proc. 48th IEEE International Midwest Symposium on Circuits and Systems, pp. 507-510, (Cincinnati, OH, August 7-10, 2005).

S. Yellampalli, A. Srivastava and V.K. Pulendra, “A combined oscillation, power supply current, and IDDQ testing methodology for fault detection in floating gate input CMOS operational amplifier,” Proc. 48th IEEE International Midwest Symposium on Circuits and Systems, pp. 503-506, (Cincinnati, OH, August 7-10, 2005).

A. Srivastava and R.R. Anantha, “A programmable oversampling sigma-delta analog-to-digital converter,” Proc. 48th IEEE International Midwest Symposium on Circuits and Systems, pp. 539-542, (Cincinnati, OH, August 7-10, 2005),

S. R. Herlekar, H.C. Wu, Chi Zhang and A. Srivastava, “Suppression of phase noise in OFDM synchronization devices using ICI self-cancellation coding,” Proc. IEEE Global Telecommunications Conference, GLOBECOM 2005, (St. Louis, MO, Nov. 28 - Dec. 2, 2005).

Chi Zhang and A. Srivastava, “Hot carrier effects on jitter and phase noise in CMOS voltage-controlled oscillators,” Proc. of SPIE - Noise in Devices and Circuits III, vol. 5844, pp. 52-62, 2005, (Austin, TX, May 23-26, 2005).

A. Srivastava, S. S. Yellampalli and V. Pulendra, “A combined noise analysis and power supply current based testing of CMOS analog integrated circuits,” Proc. of SPIE - Noise in Devices and Circuits III, vol. 5844, pp. 230-237, 2005, (Austin, TX, May 23-26, 2005).

S. R. Herlekar, Chi Zhang, H. Wu and A. Srivastava, “Phase noise analysis for OFDM systems based on hot-carrier effects in synchronization electronics,” Proc. of SPIE - Noise in Communication Systems, vol. 5847, pp. 150-159, 2005, (Austin, TX, May 23-26, 2005).

J. M. Marulanda, A. Srivastava and R.K. Nahar, “Ultra-high frequency modeling of carbon nanotube field-effect transistors (CNT-FETs), Proc. IEEE 13th International Workshop on the Physics of Semiconductor Devices (IWPSD), Dec. 13-17, 2005, Delhi.

J. M. Marulanda and A. Srivastava, “I-V characteristics modeling and parameter extraction for CN-FETs,” Proc. 2005 International Semiconductor Device Research Symposium, Dec. 7-9, 2005, MD.,