Please let me know if you change your mind about taking the exam during the alternate time.
Study recommendation: write a short program for the various ISA types (stack, accumulator, etc) using different instruction variations.
3.1-3.6, Pipelining basics, except static branch prediction.
3.7 Multicycle operations, precise exceptions.
Recommended3.5 Static branch prediction.
3.8 Instruction set design and pipelining.
3.9 MIPS R4000
3.10 Fallacies & pitfalls.
3.11 Concluding remarks.
Study RecommendationsBe sure to thoroughly understand pipeline execution diagrams and their relationship to the hardware. Look for examples in homework and exam solutions. Determine how the pipelines would have to be modified to add new instructions, and how those instructions would execute. See 1997 homework assignments 3 and 4 on previous work page.
Find pipeline execution diagrams for multicycle execution units, including those with initiation intervals greater than 1 but no larger than their latency. (A good start is to understand what 1998 homework 4, problem 1 is asking.)
4.1 Basics, dependencies.
4.2 Dynamic scheduling.
Also study PED notation used in class and on homeworks.
The distinction between dynamic scheduling using reservation stations only, using reservation stations and a reorder buffer, and using reservation stations, a reorder buffer, and rename registers is not clearly made in the book. The material is described in Set 10 and homework solutions, such as Spring 1999 homework 4.
Load/Store Units: Use for bypassing, access ordering based on address dependencies (for nonblocking caches).
4.3 Branch prediction. (Also see material in 3.5.)
Branch misprediction recovery with and without register map backup.
4.4 Multiple issue. (Superscalar and VLIW.)
Some of the material was presented in class only. For a talk describing the Intel/HP EPIC ISA (a variation on VLIW) presented in class see slides and transcript. Also be sure to study class notes, homework and exam solutions.
4.5 Loop unrolling.
4.6 Predicated execution, speculative execution using reorder buffer, etc.
Recommended4.8 PowerPC 620
4.9 Fallacies & pitfalls.
4.10 Concluding remarks.
Study RecommendationsStudy and generate pipeline execution diagrams of dynamically scheduled systems (using reservation stations and Tomasulo's algorithm). Be able to answer these questions with respect to a pipeline execution diagram and a diagram of the pipeline: When is data placed on the common data bus? Why would it be bad for instructions to pass through the MEM stage in a dynamically scheduled system? How long does an instruction occupy a reservation station, and why? Where are instruction results temporarily held and how are they named in the various dynamic scheduling techniques?
For branch prediction: When are the BHT and BTB updated? How do these affect when the branch target is fetched? How does predicated execution help? For branch prediction techniques, find programs that will work well, and programs whose branches will be frequently mispredicted.
5.1 Introduction.
5.2 Cache basics, including set-associative caches..
5.3 Miss types, effect of changing set associative cache parameters.
5.4 Reducing miss penalty. Several variations, including multi-level caches.
Also: Use of memory devices to implement main memory and caches. See Set 13, homework 6, and last year's final exam.
5.7 (If covered.) Virtual memory: virtual and real address, page tables, page faults, the TLB. Skip material on protection.
Study RecommendationsUnderstand the relationship between addresses and the memory devices used to implement main memory and caches. Try solving homework 5, problem 4 for a system using unaligned addresses. For several cache variations, figure out where data and tags would be placed for some address. Construct possible addresses for data stored at given locations in the data and tag stores of a cache. For several cache variations, try writing advocate and adversary programs that will have very high, and very low hit ratios, respectively.
David M. Koppelman - koppel@ee.lsu.edu | Modified 3 Dec 1999 11:44 (1744 UTC) |