EE 7725 Interconnection Networks - Syllabus

When/Where/How
MWF 11:40-12:30 CT Fall 1997

210 Tureaud Hall

Call Number 7077 (Fall 1997)

Instructor
David M. Koppelman

What
What do you do when the world's fastest CPU takes two days to compute the one-day weather forecast? You take ten CPU's and divide the problem between them, this is called parallel processing. The CPU's need to communicate while solving the problem; they do so using an interconnection network.

The course will describe a range of interconnection designs, concentrating on what are called multistage interconnection networks. Their use in message passing and shared memory issues will be covered; treatment ranges from theoretical foundations to implementation.

Topics

	Review of Parallel Processing
	XX	Communication in shared-memory and message-passing systems.
	XX	Parallel system models.
	Direct Networks: n-dimensional meshes and de-Bruijn families.
	MIN Basics: omega family topology and operation.
	Performance Analyses: analytic bounds, queuing models, simulation.
	Banyan and Delta Classes: topology, properties, admissible permutations.
	Fault-Tolerant and Multiple-Path Banyan-Like Networks
	Clos and Related Networks
	Generalized Connectors
	Sorting and Counting Networks.
	Congestion Reduction Techniques
	Shared Memory Topics (Time Permitting)

Texts
(Recommended, about 15% overlap with this course.) F. Thomas Leighton, "Introduction to parallel algorithms and architectures: arrays, trees, hypercubes."

Journal and Conference Papers

Grading
30% Midterm Exam; 30% Final Exam; 20% Project; 20% Homework

Late-homework and project penalty: 10% per day late deducted. Missed-midterm-exam policy: at instructor's discretion either a makeup exam, use final exam grade for midterm grade (i.e., 60% final exam weight), or use of zero for midterm grade. Attendance: optional, however students are responsible for all material, instructions, and notices presented in class.