Publications of J. Ramanujam

Research supported by

• Book Chapters
• Some recent Theses/Dissertations directed by me
• Refereed Journal Articles
• Selected Journal Articles under Review
• Conference and Workshop Papers
• Selected Technial Reports

Copyrights to the many of the following papers are held by the publishers. The attached PostScript (or PDF) files are preprints. It is understood that all persons copying this information will adhere to the terms and constraints invoked by each author's copyright. These works may not be reposted without the explicit permission of the copyright holder.

• Improving variable placement for embedded processors, by S. Atri, J. Ramanujam, and M. Kandemir. Languages and Compilers for High-Performance Computing, S. Midkiff et al., Eds., Lecture Notes in Computer Science, Springer-Verlag, 2001.

• Integer Lattice Based Methods for Local Address Generation for Block-Cyclic Distributions, by J. Ramanujam. Languages, Compilation Techniques and Run Time Systems for Scalable Parallel Systems, S. Pande and D. Agrawal, Eds., Lecture Notes in Computer Science, Springer-Verlag, 2001.

• Code restructuring for improving real-time response through code size, speed and power trade-offs on limited memory embedded DSPs, by V. Jain, S. Rele, S. Pande, and J. Ramanujam. In Languages and Compilers for Parallel Computing, L. Carter and J. Ferrante (Eds.), Lecture Notes in Computer Science, Vol. 1863, pp. 459--463, Springer-Verlag, 2000.

• An Iteration Space Transformation Algorithm Based on Explicit Data Layout Representation for Optimizing Locality, by M. Kandemir, J. Ramanujam, A. Choudhary, and P. Banerjee. In Languages and Compilers for Parallel Computing, S. Chatterjee et al., Eds., Lecture Notes in Computer Science, Springer-Verlag, 1999.

• Improving Locality in Out-of-core Computations Using Data Layout Transformations, by M. Kandemir, J. Ramanujam, and A. Choudhary. In Languages, Compilers, and Run-Time Systems for Scalable Computers, D. O'Hallaron et al., Eds., Lecture Notes in Computer Science, Volume 1511, pages 359-366, Springer-Verlag, 1998.

• Code Generation for Complex Subscripts in Data-Parallel Programs, by J. Ramanujam, Swaroop Dutta, and A. Venkatachar. In Languages and Compilers for Parallel Computing, Z. Li et al., Eds., Lecture Notes in Computer Science, Volume 1366, pages 49-63, Springer-Verlag, 1998.

• Generalized Overlap Regions for Communication Optimization in Data-Parallel Programs, by A. Venkatachar, J. Ramanujam and A. Thirumalai. In Languages and Compilers for Parallel Computing, D. Sehr et al., Eds., Lecture Notes in Computer Science, Volume 1239, pages 404-419, Springer-Verlag, 1997.

• Fast Address Sequence Generation for Data-Parallel Programs Using Integer Lattices, by A. Thirumalai and J. Ramanujam. In Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science, Volume 1033, pages 291-308, Springer-Verlag, 1996.

• Communication Generation and Optimization for HPF, by A. Thirumalai, J. Ramanujam and A. Venkatachar. In Languages, Compilers and Run-Time Systems for Scalable Computers, B. Szymanski and B. Sinharoy, Eds., Chapter 29, pages 311-316, Kluwer Academic Publishers, 1996.

• Analysis of Event Synchronization in Parallel Programs, by J. Ramanujam and A. Mathew. In Languages and Compilers for Parallel Computing, K. Pingali et al., Eds., Lecture Notes in Computer Science, Vol. 892, pages 300-315, Springer-Verlag, 1995.

• Iteration Space Tiling for Distributed Memory Machines, by J. Ramanujam and P. Sadayappan. In Languages, Compilers and Environments for Distributed Memory Machines, J. Saltz and P. Mehrotra, Eds., Amsterdam, The Netherlands: North-Holland, pages 255-270, 1992. [No figures]

• Distributed Generation of Pairwise Combinations on a Hypercube, by P. Sadayappan, F. Ercal and J. Ramanujam. In Parallel Computing 89, D. Evans, G. Joubert and F. Peters, Eds., Amsterdam, The Netherlands: North-Holland, pages 299-304, 1990.

• Compiler optimizations of subscripted variables in memory intensive applications, Satish Krishnamurthy, M.S. Thesis, Department of Electrical and Computer Engineering, Louisiana State University, May 2001.

• Techniques for relative scheduling in high-level synthesis, Kiran Bangalore, M.S. Thesis, Department of Electrical and Computer Engineering, Louisiana State University, August 2000.

• Improved code optimization techniques for embedded processors, Sunil Atri, M.S. Thesis, Department of Electrical and Computer Engineering, Louisiana State University, December 1999.

• Efficient techniques for problems in high level synthesis, Sandeep Deshpande, M.S. Thesis, Department of Electrical and Computer Engineering, Louisiana State University, August 1998.

• Exact scheduling techniques for high level synthesis, Mukund Narasimhan, M.S. Thesis, Department of Electrical and Computer Engineering, Louisiana State University, May 1998.

• Compilation and run-time techniques for data-parallel programs, Swaroop Dutta, M.S. Thesis, Department of Electrical and Computer Engineering, Louisiana State University, December 1997.

• Code generation and optimization for block-cyclic distributions, Arun Venkatachar, M.S. Thesis, Department of Electrical and Computer Engineering, Louisiana State University, December 1996.

• Automatic data and computation mapping for distributed memory machines, Isidoro Couvertier-Reyes, Ph.D. Dissertation, Department of Electrical and Computer Engineering, Louisiana State University, May 1996.

• Code generation and optimization for High Performance Fortran, Ashwath Thirumalai, M.S. Thesis, Department of Electrical and Computer Engineering, Louisiana State University, August 1995.

• Optimizing data locality and parallelism for scalable multiprocessors, Ashish Narayan, M.S. Thesis, Department of Electrical and Computer Engineering, Louisiana State University, May 1994.

• A fast approach to computing exact solutions to the resource constrained scheduling problem, by M. Narasimhan and J. Ramanujam. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2001.

• Compact and efficient code generation through program restructuring on limited memory embedded DSPs for speed, size and power trade-offs, by V. Jain, S. Rele, S. Pande, and J. Ramanujam. IEEE Transactions on Computer-Aided Design, 2001.

• A layout-conscious iteration space transformation technique, by M. Kandemir, J. Ramanujam, A. Choudhary, and P. Banerjee. IEEE Transactions on Computers, 2001.

• Data relation vectors: a new abstraction for data optimizations, by M. Kandemir and J. Ramanujam. IEEE Transactions on Computers, 2001.

• An I/O conscious tiling strategy for disk-resident data sets, by M. Kandemir, A. Choudhary, and J. Ramanujam. The Journal of Supercomputing, 2002.

• Static and dynamic locality optimizations using integer linear programming, by M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and E. Ayguade. IEEE Transactions on Parallel and Distributed Systems.

• A unified framework for optimizing locality, parallelism, and communication in out-of-core computations, by M. Kandemir, A. Choudhary, J. Ramanujam, and M. Kandaswamy. IEEE Transactions of Parallel and Distributed Systems, 2000.

• Minimizing data and synchronization costs in one-way communication, M. Kandemir, A. Choudhary, P. Banerjee, J. Ramanujam, and N. Shenoy. IEEE Transactions of Parallel and Distributed Systems, 2000.

• Mapping by Adaptive Simulated Annealing, by J. Ramanujam, F. Ercal and P. Sadayappan. Parallel Computing.

• Compiler algorithms for optimizing locality and parallelism on shared and distributed memory machines, by M. Kandemir, J. Ramanujam, and A. Choudhary. Journal of Parallel and Distributed Computing, August 2000.

• A global communication optimization technique based on dataflow analysis and linear algebra, by M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and N. Shenoy. ACM Transactions on Programming Languages and Systems, 1999.

• A matrix-based approach to global locality optimization, by M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee. In Journal of Parallel and Distributed Computing, September 1999.

• A linear algebra framework for automatic determination of optimal data layouts, by M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, and J. Ramanujam. IEEE Transactions of Parallel and Distributed Systems, 1999.

• Improving cache locality by a combination of loop and data transformations, by M. Kandemir, J. Ramanujam, and A. Choudhary. IEEE Transactions on Computers, February 1999.

• Partitioning Graphs on Message-Passing Machines by Pairwise Mincut, by P. Sadayappan, F. Ercal and J. Ramanujam. Information Sciences, 111(1-4):223-237, October 1998.

• Compilation Techniques for Out-of-Core Parallel Computations, by M. Kandemir, A. Choudhary, J. Ramanujam and R. Bordawekar. Parallel Computing, 24(3-4):597-628, June 1998.

• Locality Optimization Algorithms for Compilation of Out-of-Core Codes, by M. Kandemir, A. Choudhary, J. Ramanujam and M. Kandaswamy. Journal of Information Science and Engineering, 14(1):107-138, March 1998.

• Communication Generation for Block-Cyclic Distributions, by A. Venkatachar, J. Ramanujam, and A. Thirumalai. Parallel Processing Letters, 7(2), pages 195-202, June 1997.

• Efficient Computation of Address Sequences in Data-Parallel Programs Using Closed Forms for Basis Vectors, by A. Thirumalai and J. Ramanujam. Journal of Parallel and Distributed Computing, 38(2), pages 188-203, November 1996.

• Compilation and Communication Strategies for Out-of-core programs on Distributed Memory Machines, by Rajesh Bordawekar, Alok Choudhary and J. Ramanujam. CACR SIO Technical Report 113, CalTech. Journal of Parallel and Distributed Computing, 38(2), pages 277-288, November 1996.

• A Neural Architecture for a Class of Abduction Problems, by A. Goel and J. Ramanujam. IEEE Transactions on Systems Man and Cybernetics, 26(6), pages 854-860, December 1996. An earlier version of the paper is available.

• Efficient Algorithms for Array Redistribution, by R. Thakur, A. Choudhary and J. Ramanujam. IEEE Transactions on Parallel and Distributed Systems, 7(6), pages 587-594, June 1996.

• Beyond Unimodular Transformations, by J. Ramanujam. The Journal of Supercomputing, 9(4), pages 365-389, October 1995. [No figures]; HTML version of paper.

• Mapping Combinatorial Optimization Problems onto Neural Networks, by J. Ramanujam and P. Sadayappan. Information Sciences, 82(3/4), pages 239-255, January 1995.

• Tiling Multidimensional Iteration Spaces for Multicomputers, by J. Ramanujam and P. Sadayappan. Journal of Parallel and Distributed Computing, 16(2), pages 108-120, October 1992. [No figures]

• Compile-Time Techniques for Data Distribution in Distributed Memory Machines, by J. Ramanujam and P. Sadayappan. IEEE Transactions on Parallel and Distributed Systems, 2(4), pages 472-482, October 1991. [No figures]

• Task Allocation by Recursive Mincut Bipartitioning onto a Hypercube, by F. Ercal, J. Ramanujam and P. Sadayappan. Journal of Parallel and Distributed Computing, 10(1), pages 35-44, September 1990. [No figures]

• Cluster Partitioning Approaches to Mapping Parallel Programs onto a Hypercube, by F. Ercal, P. Sadayappan and J. Ramanujam. Parallel Computing, 13(1), pages 1-16, March 1990. [No figures]

• Address Sequence Generation for Data-Parallel Programs Using Integer Lattices, by A. Thirumalai and J. Ramanujam.

• Multi-Phase Redistribution: A Communication-Efficient Approach to Array Redistribution, by S. D. Kaushik, C.-H. Huang, J. Ramanujam, and P. Sadayappan. A longer version is available as an Ohio State University CIS Technical Report.

• Software Pipelining of Nested Loops, by J. Ramanujam. HTML version of paper.

• Compiler support for block buffering, by M. Kandemir, J. Ramanujam, and U. Sezer. Proc. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'01), Huntington Beach, CA, August 2001.

• Morphable Cache Architectures: Potential Benefits, by I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and J. Ramanujam. Proc. ACM SIGPLAN 2001 Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES'2001), Snowbird, UT, June 2001.

• Reducing memory requirements of nested loops for embedded systems, by J. Ramanujam, J. Hong, M. Kandemir, and A. Narayan. Proc. 38th Design Automation Conference, Las Vegas, NV, June 2001.

• Dynamic management of scratch-pad memory space, by M. Kandemir, J. Ramanujam, M. Irwin, V. Narayanan, I. Kadayif, and A. Parikh. Proc. 38th Design Automation Conference, Las Vegas, NV, June 2001.

• Loop optimization for a class of memory-constrained computations, by D. Cociorva, J. Wilkins, C.-C. Lam, G. Baumgartner, P. Sadayappan, and J. Ramanujam. Proc. 15th ACM International Conference on Supercomputing (ICS'01), Sorrento, Italy, June 2001.

• Address register-oriented optimizations for embedded processors, by J. Ramanujam, J. Hong, M. Kandemir, and S. Atri. Proc. 9th Workshop on Compilers for Parallel Computers (CPC 2001), Edinburgh, Scotland, June 2001.

• A new variable placement algorithm for embedded processors, by S. Atri, J. Ramanujam, and M. Kandemir. In Proc. International Conference on High Performance Computing (HiPC'00), Bangalore, India December 17-20, 2000.

• Data relation vectors: a new abstraction for data optimizations, by M. Kandemir and J. Ramanujam. In Proc. International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, PA, October 2000.

• On lower bounds for scheduling problems in high-level synthesis, by M. Narasimhan and J. Ramanujam. In Proc. 37th Design Automation Conference, Los Angeles, CA, pages 546-551, June 2000.

• On reducing false sharing while improving locality on shared memory multiprocessors, by M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee. In Proc. International Conference on Parallel Architectures and Compilation Techniques (PACT'99), Newport Beach, CA, October 1999.

• A framework for interprocedural locality optimization using both loop and data layout transformations, by M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee. In Proc. 1999 International Conference on Parallel Processing, Aizu, Japan, September 1999.

• Compiler optimizations for I/O intensive computations, by M. Kandemir, A. Choudhary, and J. Ramanujam. In Proc. 1999 International Conference on Parallel Processing, Aizu, Japan, September 1999.

• I/O conscious tiling for disk-resident data sets, by M. Kandemir, A. Choudhary, and J. Ramanujam. Proc. Euro-Par'99, France, September 1999.

• An integer linear programming approach to optimizing cache locality, by M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and E. Ayguade. In Proc. ACM International Conference on Supercomputing (ICS 99), Greece, June 1999.

• A Graph-based Framework to Detect Optimal Memory Layouts for Improving Data Locality, by M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee. Proc. 1999 International Parallel Processing Symposium, April 1999.

• Efficient Address Sequence Generation for Two-level Mappings in High Performance Fortran, by J. Ramanujam, A. Venkatachar, and S. Dutta. In Proc. 1998 International Conference on High Performance Computing, Chennai, India, December 1998.

• Improving the Computational Efficiency of ILP-based Problems, by M. Narasimhan and J. Ramanujam. In Proc. International Conference on Computer Aided Design (ICCAD-98), San Jose, CA, November 1998.

• A Matrix-Based Approach to the Global Locality Optimization Problem, by M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee. In Proc. International Conference on Parallel Architectures and Compilation Techniques (PACT'98), Paris, France, October 1998.

• Enhancing spatial locality via data layout optimizations, M. Kandemir, A. Choudhary, J. Ramanujam, N. Shenoy, and P. Banerjee. In Proc. Euro-Par'98 (Workshop on Automatic Parallelisation), Southampton, UK, September 1998.

• Minimizing data and synchronization costs in one-way communication, M. Kandemir, N. Shenoy, P. Banerjee, J. Ramanujam, and A. Choudhary. In Proc. 1998 International Conference on Parallel Processing, Minneapolis, MN, August 1998.

• A hyperplane based approach for optimizing spatial locality in loop nests, M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, and J. Ramanujam. In Proc. 1998 ACM International Conference on Supercomputing, Melbourne, Australia, pages 69-76, July 1998.

• Advanced compilation techniques for HPF, J. Ramanujam, S. Dutta, A. Venkatachar, and A. Thirumalai. In Proc. 7th International Workshop on Compilers for Parallel Computers, Linkoping, Sweden, June 1998.

• Optimizing spatial locality in loop nests using linear algebra, M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee. In Proc. 7th International Workshop on Compilers for Parallel Computers, Linkoping, Sweden, June 1998.

• Improving locality in out-of-core computations using data layout transformations, M. Kandemir, A. Choudhary, and J. Ramanujam. In Proc. 4th Workshop on Languages, Compilers, and Run-Time Systems for Scalable Computers, Pittsburgh, PA, May 1998.

• A generalized framework for global communication optimization, M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and N. Shenoy. In Proc. 1998 International Parallel Processing Symposium, pages 69-73, March 1998.

• Compiler Algorithms for Optimizing Locality and Parallelism on Shared and Distributed Memory Machines, by M. Kandemir, J. Ramanujam and A. Choudhary. In Proc. 1997 International Conference on Parallel Architectures and Compilation Techniques (PACT 97), pages 236-247, San Francisco, CA, November 1997.

• A Unified Compiler Algorithm for Optimizing Locality, Parallelism and Communication in Out-of-Core Computations, by M. Kandemir, A. Choudhary, J. Ramanujam and M. Kandaswamy. In Proc. IOPADS '97: Workshop on I/O in Parallel and Distributed Systems, co-located with SC97 in San Jose, CA, pages 79-92, November 1997.

• Optimizing Out-of-Core Computations using Chain Vectors, by M. Kandemir, J. Ramanujam and A. Choudhary. In Proc. Euro-Par'97, Lecture Notes in Computer Science, Volume 1300, pages 601-608, Springer-Verlag, Passau, Germany, August 1997.

• Improving the Performance of Out-of-Core Computations, by M. Kandemir, J. Ramanujam and A. Choudhary. In Proc. 1997 International Conference on Parallel Processing, pages 128-136, Bloomingdale, IL, August 1997.

• A Compiler Algorithm for Optimizing Locality in Loop Nests, by M. Kandemir, J. Ramanujam and A. Choudhary. In Proc. 11th ACM International Conference on Supercomputing, pages 269-278, Vienna, Austria, July 1997.

• Optimizing Out-of-Core Computations in Uniprocessors, by M. Kandemir, A. Choudhary, J. Ramanujam and R. Bordawekar. In Proc. Workshop on Architecture-Compiler Interaction, 3rd HPCA, San Antonio, TX, February 1997.

• Data Structures for Efficient Execution of Programs with Block-Cyclic Distributions, by S. Dutta and J. Ramanujam. In Proc. Sixth International Workshop on Compilers for Parallel Computers (CPC 96), Aachen, Germany, December 1996.

• A Unified Tiling Approach for Out-of-Core Computations, by M. Kandemir, R. Bordawekar, A. Choudhary and J. Ramanujam. In Proc. Sixth International Workshop on Compilers for Parallel Computers (CPC 96), Aachen, Germany, December 1996.

• A Framework for Integrating Communication and I/O Placement, by Rajesh Bordawekar, Alok Choudhary and J. Ramanujam. In Proc. EUROPAR-96, Lyon, France, August 1996.

• Automatic Optimization of Communication in Out-of-core Stencil Codes, by Rajesh Bordawekar, Alok Choudhary and J. Ramanujam. In Proc. 10th ACM International Conference on Supercomputing, Philadelphia, PA, May 1996.

• An Efficient Compile-Time Approach to Compute Address Sequences in Data Parallel Programs, by A. Thirumalai and J. Ramanujam. In Proc. 5th International Workshop on Compilers for Parallel Computers, Malaga, Spain, pages 581-605, June 1995.

• HPF Array Statements: Communication Generation and Optimization, by A. Thirumalai and J. Ramanujam (Preliminary version). 3rd Workshop on Languages, Compilers and Run-Time Systems for Scalable Computers, Troy, NY, May 1995.

• Automatic Data Mapping and Program Transformations, by J. Ramanujam and A. Narayan. In Proc. Workshop on Automatic Data Layout and Performance Prediction, Houston, TX, April 1995.

• Statement-Level Independent Partitioning of Uniform Recurrences, by J. Ramanujam and S. Vasanthakumar. In Proc. 9th International Parallel Processing Symposium, pages 229-233, April 1995.

• Multi-Phase Array Redistribution: Modeling and Evaluation, by S. D. Kaushik, C.-H. Huang, J. Ramanujam, and P. Sadayappan. In Proc. 9th International Parallel Processing Symposium, pages 441-445, April 1995.

• Integrating Data Distribution and Loop Transformations for Distributed Memory Machines, by J. Ramanujam and A. Narayan. In Proc. 7th SIAM Conference on Parallel Processing for Scientific Computing, D. Bailey, et al., Eds., pages 668-673, SIAM Press, 1995. Talk Slides in Postscript; HTML version of paper.

• Optimal Software Pipelining of Nested Loops, by J. Ramanujam. In Proc. 8th International Parallel Processing Symposium, (April 1994), pages 335-342.

• Non-Unimodular Transformations of Nested Loops, by J. Ramanujam. In Proc. Supercomputing 92, (November 1992), pages 214-223. [No figures]

• A Linear Algebraic View of Loop Transformations and their Interaction, by J. Ramanujam. In Proc. 5th SIAM Conference on Parallel Processing for Scientific Computing, D. Sorensen, Ed., SIAM Press, pages 543-548, 1992.

• Multidimensional Iteration Space Tiling for Nonshared Memory Machines, by J. Ramanujam and P. Sadayappan. In Proc. Supercomputing 91, (November 1991), pages 111-120. [No figures]

• Access Based Data Decomposition in Distributed Memory Machines, by J. Ramanujam and P. Sadayappan. In Proc. 6th Distributed Memory Computing Conference, (April 1991), pages 196-199. [No figures]

• Tiling of Iteration Spaces for Multicomputers, by J. Ramanujam and P. Sadayappan. In Proc. 1990 International Conference on Parallel Processing, (August 1990), vol. II, pages 179-186. [No figures]

• Nested Loop Tiling for Distributed Memory Machines, by J. Ramanujam and P. Sadayappan. In Proc. 5th Distributed Memory Computing Conference, (Charleston, SC, April 1990), pages 1088-1096.

• A Methodology for Parallelizing Programs for Multicomputrs and Complex Memory Multiprocessors, by J. Ramanujam and P. Sadayappan. In Proceedings of Supercomputing 89, (Reno, NV, Nov. 1989), pages 637-646. [No figures]

• Parallel Graph Partitioning on a Hypercube, by F. Ercal, P. Sadayappan and J. Ramanujam. In Proceedings of the 4th Hypercube Concurrent Computers and Applications Conference, (March 1989), vol. 1, pages 67-70.

• Task Allocation by Simulated Annealing, by J. Ramanujam, F. Ercal and P. Sadayappan. In Proceedings of the 3rd International Conference on Supercomputing, (Boston, MA, May 1988), vol. 3, pages 471-480.

• Task Allocation onto a Hypercube by Recursive Mincut Bipartitioning, by F. Ercal, J. Ramanujam and P. Sadayappan. In Proceedings of the 3rd Hypercube Concurrent Computers and Applications Conference, (Pasadena, CA, January 1988), pages 210-221.

• Optimization Using Neural Networks, by J. Ramanujam and P. Sadayappan. In Proceedings of IEEE 2nd International Conference on Neural Networks, (San Diego, CA, July, 1988), vol. 2, pages 325-332.

• Towards a Neural Architecture for Abductive Reasoning, by A. Goel, J. Ramanujam and P. Sadayappan. In Proceedings of IEEE 2nd International Conference on Neural Networks, (San Diego, CA, July, 1988), vol. 1, pages 681-688.

• Parameter Identification for Constrained Optimization Using Neural Networks, by J. Ramanujam and P. Sadayappan. In Proceedings of 1988 Connectionist Models Summer School, (Carnegie Mellon University, Pittsburgh, PA, June 1988), San Mateo, CA: Morgan Kaufman, pages 154-161.

• Enhancing spatial locality using data layout optimizations, M. Kandemir, A. Choudhary, J. Ramanujam, N. Shenoy, and P. Banerjee. Technical Report, CPDC-TR-97-07, Northwestern University, December 1997.

• Experiments with data layouts, M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, and J. Ramanujam. Technical Report, CPDC-TR-97-06, Northwestern University, December 1997. (Addendum to CPDC-TR-97-04, December 1997)

• A data layout optimization technique based on hyperplanes, M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, and J. Ramanujam. Technical Report, CPDC-TR-97-04, Northwestern University, December 1997.

• A combined communication and synchronization optimization algorithm for one-way communication, M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and N. Shenoy. Technical Report, CPDC-TR-97-03, Northwestern University, October 1997.

• Optimizing communication using global data flow analysis, M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and N. Shenoy. Technical Report, CPDC-TR-97-02, Northwestern University, October 1997.

• Tighter lower bounds for scheduling problems in high-level synthesis, M. Narasimhan, and J. Ramanujam. Technical Report, Louisiana State University, August 1997.