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Lu Peng Assistant Professor |
Computer Architecture,
Microarchitecture, System Performance Analysis, Network Processor
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Spring
2010, EE4770 Real-Time Computing System
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Fall
2009, EE7728 Multiprocessor Computer System Design
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Fall
2009, EE4700-1 Parallel Programming
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Spring 2009, EE7720 Advanced Computer Architecture
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Spring 2009, EE2730 Digital Logic II (See LSU-Moodle)
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Fall 2008, EE7700-1 Topics in Processor Design
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Spring
2008, EE7720 Advanced Computer Architecture
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Fall
2007, EE4700-1 Parallel Programming
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Spring
2007, EE7700-2 Topics in Processor Design
· Fall 2006, EE7720 Advanced Computer Architecture
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Spring
2006, EE7000-7 Topics in Processor
Design
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Fall
2005, EE7700-2 Computer Architecture Principles
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Ph.D.,
Computer Engineering,
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M.E.,
Computer Science & Engineering,
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B.E.,
Computer Science & Engineering,
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Assistant
Professor, ECE dept., LSU Jul.
2005 - Now
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Research Intern, Intel Microarchitecture Research Lab /
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Research
Assistant,
Refereed Journal Publications:
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Y.
Zhang, L. Peng, W. Lu, L. Duan and S. Rai, “Expediating IP Lookups with Reduced Power via TBM and SST
Supernode Caching,” Accepted by Computer
Communications. (pdf)
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B.
Li, L. Peng and B. Ramadass. "Accurate and Efficient Processor Performance
Prediction via Regression Tree Based Modeling". Accepted by Journal of Systems Architecture. (pdf)
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Q.
Yu, B. Li, Z.
Fang and L. Peng, “An adaptive sampling scheme guided by BART - with an
application to predict processor performance,” Accepted by Canadian Journal of Statistics. (pdf)
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B.
Li, L. Duan and L. Peng, "Efficient Microarchitectural
Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions,"
Accepted by IEEE Transactions on
Computers, Special Issue on System Level Design of Reliable Architectures.
(pdf)
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L.
Yang, L. Peng and B. Ramadass, “SecCMP: Enhancing Critical Secret
Protection in Chip-Multiprocessors,” In International Journal of Information Security and Privacy, vol.2(4),
page 54-66, Oct.-Dec. 2008. (pdf)
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L.
Peng, J-K. Peir, T. K. Prakash, C. Staelin, Y-K.
Chen, D. Koppelman, “Memory Hierarchy Performance Measurement of
Commercial Dual-Core Desktop Processors”, In Journal of Systems Architecture, vol
54(8), Aug. 2008, page 816-828. (pdf)
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T.
K. Prakash and L. Peng, “Performance
Characterization of SPEC CPU2006 Benchmarks on Intel Core 2 Duo
Processor,” In ISAST Transactions on Computers and Software
Engineering, No. 1, Vol 2, 2008, page 36-41. (pdf)
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L.
Peng, J-K. Peir and K. Lai, "A New Memory Hierarchy Layer for Zero-cycle
Load". In Journal of
Instruction-Level Parallelism, vol.6, Sept. 2004. (acceptance
rate: 15%) (pdf)
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L.
Peng, J-K. Peir, Q. Ma and K. Lai, "Address-Free Memory Access Based on
Program Syntax Correlation of Loads and Stores", In IEEE Transactions
on VLSI systems, June, 2003. (Invited Paper) (pdf)
Refereed Conference and Workshop Papers:
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S.
Verma, D. Koppelman and L. Peng, “A Hybrid Adaptive Feedback Based
Prefetcher,” in Proceeding of the
1st JILP Data Prefetching Championship (DPC-1) in conjunction with HPCA-15, Raleigh, NC, Feb. 2009. (pdf)
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G.
Liu, Z. Huang, J-K. Peir, X. Shi and L. Peng, “Enhancement for Accurate
Stream Prefetching,” in Proceeding
of the 1st JILP Data Prefetching Championship (DPC-1) in conjunction with HPCA-15, Raleigh, NC, Feb. 2009. (pdf)
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L.
Duan, B. Li and L. Peng, “Versatile Prediction and Fast Estimation of
Architectural Vulnerability Factor from Processor Performance Metrics,”
In Proceeding of the 15th IEEE
International Symposium on High-Performance Computer Architecture (HPCA-15),
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R.
Tao, L. Yang, L. Peng, B. Li and A. Cemerlic,
“A Case Study: Using Architectural Features to Improve Sophisticated
Denial-of-Service Attack Detections,” In Proceeding of the 2009 IEEE Symposium on Computational Intelligence in
Cyber Security, Nashville, TN, Mar. 2009. (pdf)
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B.
Li, L. Peng and B. Ramadass, “Efficient MART-Aided Modeling for
Microarchitecture Design Space Exploration and Performance Prediction,”
(extended abstract), In Proceedings of 2008 ACM International Conference on
Measurement and Modeling of Computer Systems (SIGMETRICS), Annapolis, MD, Jun. 2008. (pdf)
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L. Peng, W. Lu and L. Duan, “Power
Efficient IP Lookup with Supernode Caching,” In Proceedings of the 50th IEEE Global
Communications Conference (Globecom),
Washington, DC, Nov. 2007. (pdf)
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L.
Peng, J-K. Peir, T. K. Prakash, Y-K. Chen, D.
Koppelman, “Memory Performance and Scalability of Intel's
and AMD's Dual-Core Processors: A Case Study,” In Proceedings of the 26th IEEE International
Performance Computing and Communications Conference (IPCCC),
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L.
Yang, L. Peng, “SecCMP: A Secure Chip-Multiprocessor Architecture,”
In Proceedings of the First Workshop
on Architectural and System Support for Improving Software Dependability (ASID)
in conjunction with ACM ASPLOS XII, San Jose, CA, Oct. 2006. (pdf)
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X.
Shi, Z. Yang, J-K. Peir, L. Peng, Y-K. Chen, V. Lee, and B. Liang, "Coterminous
Locality and Coterminous Group Data Prefetching on Chip-Multiprocessors",
In Proceedings of the 20th IEEE
International Parallel &
Distributed Processing Symposium (IPDPS),
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L.
Peng, J-K. Peir and K. Lai, "Signature Buffer: Bridging Performance Gap
between Registers and Caches", In Proceedings of the 10th
IEEE International Symposium on High Performance Computer Architecture
(HPCA-10),
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L.
Peng, J. Song, S. Ge, Y-K. Chen, V. Lee, J-K. Peir, and B. Liang, "Case
Studies: Memory Behavior of Multithreaded Multimedia and AI Applications",
In Proceedings of Seventh Workshop on Computer Architecture Evaluation using
Commercial Workloads (CAECW-7) in
conjunction with IEEE HPCA-10,
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Q.
Ma, J-K. Peir, L. Peng and K. Lai, "Symbolic Cache: Fast Memory Access
Based on Program Syntax Correlation of Loads and Stores", Best Paper Award, In Proceedings of
IEEE International Conference on Computer Design'01 (ICCD'01),