Lu Peng Assistant Professor Address: Louisiana State University      Dept. of Elect. & Computer Eng. Baton Rouge, LA 70803-5901 Tel:      225-578-5535 Fax:     225-578-5200 E-mail: lpeng@lsu.edu

Research Interests

Computer Architecture, Microarchitecture, System Performance Analysis, Network Processor

Teaching

· Spring 2010, EE4770 Real-Time Computing System

· Fall 2009, EE7728 Multiprocessor Computer System Design

· Fall 2009, EE4700-1 Parallel Programming

· Spring 2009, EE7720 Advanced Computer Architecture

· Spring 2009, EE2730 Digital Logic II (See LSU-Moodle)

· Fall 2008, EE7700-1 Topics in Processor Design

· Spring 2008, EE7720 Advanced Computer Architecture

· Fall 2007, EE4700-1 Parallel Programming

· Spring 2007, EE7700-2 Topics in Processor Design

· Fall 2006, EE7720 Advanced Computer Architecture

· Spring 2006, EE7000-7 Topics in Processor Design

· Fall 2005, EE7700-2 Computer Architecture Principles

Education

· Ph.D., Computer Engineering, University of Florida.

· M.E., Computer Science & Engineering, Shanghai Jiaotong University, China.

· B.E., Computer Science & Engineering, Shanghai Jiaotong University, China.

Experience

· Assistant Professor, ECE dept., LSU · Research Intern, Intel Microarchitecture Research Lab / China Research Center · Research Assistant, University of Florida

Jul. 2005 - Now Jun. 2003 - Nov. 2003 Jan. 2001 - Apr. 2005

Grants

· Louisiana State University, Faculty Research Grant, 2006-2007

· Louisiana Board of Regents, Research Competitiveness Subprogram, 2006-2009

· Louisiana BoR, NSF-EPSCoR, PFund, 2006-2007

· Louisiana State University, Summer Stipend Grant, 2007

· ORAU Ralph E. Powe Junior Faculty Enhancement Awards, 2007

· Louisiana Board of Regents, Traditional Enhancement Program, 2007-2008 (Co-PI)

· Louisiana State University, Faculty Research Grant, 2008-2009

· Louisiana BoR, NSF-EPSCoR, PFund, 2009-2010

· Louisiana Board of Regents, Traditional Enhancement Program, 2009-2010 (Co-PI)

Publications

Book Chapters:

1. L. Peng, L. Yang and B. Ramadass, “Architectural Support for Enhancing Critical Secrets Protection in Chip-Multiprocessors,” To appear in “Pervasive Information Security and Privacy Developments: Trends and Advancements,” Jun. 2010.

Refereed Journal Publications:

2. B. Li, L. Duan and L. Peng, "Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions," Accepted by IEEE Transactions on Computers, Special Issue on System Level Design of Reliable Architectures. (pdf)

3. Q. Yu, B. Li, Z. Fang and L. Peng, “An adaptive sampling scheme guided by BART - with an application to predict processor performance,” In Canadian Journal of Statistics, Vol 38(1), Mar. 2010. (pdf)

4. Y. Zhang, L. Peng, W. Lu, L. Duan and S. Rai, “Expediating IP Lookups with Reduced Power via TBM and SST Supernode Caching,” In Computer Communications, vol 33(3), pages 390-397, Feb. 2010. (pdf)

5. B. Li, L. Peng and B. Ramadass. "Accurate and Efficient Processor Performance Prediction via Regression Tree Based Modeling". In Journal of Systems Architecture. Vol. 55 (10-12), Pages 457-467, Oct.-Dec., 2009 (pdf)

6. L. Yang, L. Peng and B. Ramadass, “SecCMP: Enhancing Critical Secret Protection in Chip-Multiprocessors,” In International Journal of Information Security and Privacy, vol.2(4), page 54-66, Oct.-Dec. 2008. (pdf)

7. L. Peng, J-K. Peir, T. K. Prakash, C. Staelin, Y-K. Chen, D. Koppelman, “Memory Hierarchy Performance Measurement of Commercial Dual-Core Desktop Processors”, In Journal of Systems Architecture, vol 54(8), page 816-828, Aug. 2008. (pdf)

8. T. K. Prakash and L. Peng, “Performance Characterization of SPEC CPU2006 Benchmarks on Intel Core 2 Duo Processor,” In ISAST Transactions on Computers and Software Engineering, No. 1, Vol 2, 2008, page 36-41. (pdf)

9. L. Peng, J-K. Peir and K. Lai, "A New Memory Hierarchy Layer for Zero-cycle Load". In Journal of Instruction-Level Parallelism, vol.6, Sept. 2004. (acceptance rate: 15%) (pdf)

10. L. Peng, J-K. Peir, Q. Ma and K. Lai, "Address-Free Memory Access Based on Program Syntax Correlation of Loads and Stores", In IEEE Transactions on VLSI systems, June, 2003. (Invited Paper) (pdf)

Refereed Conference and Workshop Papers:

11. J. Chen, Z. Huang, F. Su, J.-K. Peir, J. Ho and L. Peng, “Weak Execution Ordering - Exploiting Iterative Methods on Many-Core GPUs,” In Proceedings of The 2010 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), White Plains, NY, Mar. 2010. (pdf)

12. L. Duan, B. Li and L. Peng, “Reliability-Constrained Processor Performance Optimization via Design Parameter Selection,” In Poster session of The 18^th IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), Raleigh, NC, Sep. 2009. (pdf)

13. S. Verma, D. Koppelman and L. Peng, “A Hybrid Adaptive Feedback Based Prefetcher,” in Proceedings of the 1st JILP Data Prefetching Championship (DPC-1) in conjunction with HPCA-15, Raleigh, NC, Feb. 2009. (pdf)

14. G. Liu, Z. Huang, J-K. Peir, X. Shi and L. Peng, “Enhancement for Accurate Stream Prefetching,” in Proceedings of the 1st JILP Data Prefetching Championship (DPC-1) in conjunction with HPCA-15, Raleigh, NC, Feb. 2009. (pdf)

15. L. Duan, B. Li and L. Peng, “Versatile Prediction and Fast Estimation of Architectural Vulnerability Factor from Processor Performance Metrics,” In Proceedings of the 15^th IEEE International Symposium on High-Performance Computer Architecture (HPCA-15), Raleigh, NC, Feb. 2009. (Acceptance rate: 35 / 184 = 19%) (pdf)

16. R. Tao, L. Yang, L. Peng, B. Li and A. Cemerlic, “A Case Study: Using Architectural Features to Improve Sophisticated Denial-of-Service Attack Detections,” In Proceedinsg of the 2009 IEEE Symposium on Computational Intelligence in Cyber Security, Nashville, TN, Mar. 2009. (pdf)

17. B. Li, L. Peng and B. Ramadass, “Efficient MART-Aided Modeling for Microarchitecture Design Space Exploration and Performance Prediction,” (extended abstract), In Proceedings of 2008 ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Annapolis, MD, Jun. 2008. (pdf)

18. L. Peng, W. Lu and L. Duan, “Power Efficient IP Lookup with Supernode Caching,” In Proceedings of the 50^th IEEE Global Communications Conference (Globecom), Washington, DC, Nov. 2007. (pdf)

19. L. Peng, J-K. Peir, T. K. Prakash, Y-K. Chen, D. Koppelman, “Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study,” In Proceedings of the 26^th IEEE International Performance Computing and Communications Conference (IPCCC), New Orleans, LA, Apr. 2007. (pdf)

20. L. Yang, L. Peng, “SecCMP: A Secure Chip-Multiprocessor Architecture,” In Proceedings of the First Workshop on Architectural and System Support for Improving Software Dependability (ASID) in conjunction with ACM ASPLOS XII, San Jose, CA, Oct. 2006. (pdf)

21. X. Shi, Z. Yang, J-K. Peir, L. Peng, Y-K. Chen, V. Lee, and B. Liang, "Coterminous Locality and Coterminous Group Data Prefetching on Chip-Multiprocessors", In Proceedings of the 20^th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Rhodes Island, Greece. Apr. 2006. (acceptance rate: 24%) (pdf)

22. L. Peng, J-K. Peir and K. Lai, "Signature Buffer: Bridging Performance Gap between Registers and Caches", In Proceedings of the 10^th IEEE International Symposium on High Performance Computer Architecture (HPCA-10), Madrid, Spain, Feb. 2004. (acceptance rate: 17%) (pdf)

23. L. Peng, J. Song, S. Ge, Y-K. Chen, V. Lee, J-K. Peir, and B. Liang, "Case Studies: Memory Behavior of Multithreaded Multimedia and AI Applications", In Proceedings of Seventh Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-7) in conjunction with IEEE HPCA-10, Madrid, Spain, Feb. 2004. (pdf)

24. Q. Ma, J-K. Peir, L. Peng and K. Lai, "Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores", Best Paper Award, Processor Architecture Track, In Proceedings of IEEE International Conference on Computer Design'01 (ICCD'01), Austin, TX, Sept. 2001. (pdf)

Processional Services

· Program Committee Member, The 28th IEEE International Performance Computing and Communications Conference

· Program Committee Member, The 9th IASTED International Conference on Parallel and Distributed Computing and Networks

· Program Committee Member, The 21st IASTED International Conference on Parallel and Distributed Computing and Systems

· Program Committee Member, The 10th IEEE International Symposium on Pervasive Systems, Algorithms and Networks

· Program Committee Member, 2009 IASTED International Conference on Parallel and Distributed Computing and Networks.

· Program Committee Member, The 20th IASTED International Conference on Parallel and Distributed Computing and Systems.

· Program Committee Member, International Conference on Parallel Processing 2008.

· Program Committee Member, International Conference on Parallel Processing 2007.

· Session Chair, International Performance Computing and Communications Conference, 2007.

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