EE 7760 Reliable Design of Digital Systems

General: Units 3 hrs.

Catalog Description

Prereq: EE3720 or equivalent.

Test generation for combinational and sequential circuits, self-checking circuits, fault tolerant design, design for testability, and topics in LSI testing.

Reference Books

  1. M. Abramivici, M. A. Breuer, and A. D. Friedman, Digital systems testing and testable design , Computer Science Press (1990).
  2. N. K. Jha and S. Kundu, Testing and reliable design of CMOS circuits , Kluwer Publications (1990).
  3. A. J. vande Goor, Testing semiconductor memories, John-Wiley (1991)
Goals: To give the students an acquaintance with TTL and CMOS circuit testing and design for testability.

Topics

  1. Physical failures at switch level in TTL and CMOS circuits, logical fault model, single and multiple stuck at model, bridging faults, stuck open and stuck on type model, faults in PLAs and memories, static and dynamic hazards.
  2. Test generation for combinational circuits, fault equivalence, dominance, collapsing, Boolean differences for single and multiple stuck at faults, path sensitization, D-algorithm, PODEM, FAN, neural network; Use of MODEM and NNET tools in ATPG.
  3. Test generation experiments for sequential circuits, random testing, transition counting.
  4. LSI testing, PLAs and memories, RAM and ROM, functional and behavioral testing.
  5. Reliable design, self-checking circuits, redundancy schemes, syndrome testing, signature analysis, aliasing, design for testability.
  6. Other topics of interest, logic and fault simulation.