// Code for LSU EE 4702-1 Spring 2000. // Differences in handling of case statements. // See also case2.v // The comments discussed the RTL inferred by Leonardo Spectrum 1999.1f, // which can be viewed by selecting View RTL Schematic from the Tools // menu of the GUI. // The module below instantiates three other modules in this file. // The synthesis program will synthesize the module below and the // modules it instantiates. module simple(x1, x2, x3, sel, a, b, c, d); input sel, a, b, c, d; output x1, x2, x3; wire [2:0] sel; wire x1, x2, x3, a, b, c, d; simple_2bit s_2bit(x1,sel,a,b,c,d); simple_3bit s_3bit(x2,sel,a,b,c,d); selcase s_sc(x3,sel,a,b,c,d); endmodule // simple module simple_2bit(x,sel,a,b,c,d); input sel, a, b, c, d; output x; wire [1:0] sel; reg x; wire a, b, c, d; // A four-input multiplexor. The synthesis program will correctly // infer the four-input multiplexor from the code below. always @( sel or a or b or c or d ) case( sel ) 0: x = a; 1: x = b; 2: x = c; 3: x = d; endcase endmodule module simple_3bit(x,sel,a,b,c,d); input sel, a, b, c, d; output x; wire [2:0] sel; reg x; wire a, b, c, d; // A four-input multiplexor with a 3-bit select input. The code // below describes a module that remembers the output the last // time sel was less than four. (When sel is less than 4 it works // as an ordinary multiplexor.) The synthesis program must insert // a latch to get this behavior. Of course, it's possible that // the engineer intended the sel input to be two bits but made a // typo. always @( sel or a or b or c or d ) case( sel ) 0: x = a; 1: x = b; 2: x = c; 3: x = d; endcase endmodule module selcase(x,sel,a,b,c,d); input sel, a, b, c, d; output x; wire [1:0] sel; reg x; wire a, b, c, d; // This code is functionally equivalent to simple_2bit, but uses // comparisons in the case items. The synthesis program is not // able to infer that this is a multiplexor (with a binary select // input). Instead it synthesizes a data selector and four // comparators (sel==0, sel==1, etc.). It is able to determine // that the case items are mutually exclusive but it can't // determine that one of them will always be true. (See case2.v // for more on this.) Therefore it will include a latch. Unlike // simple_3bit, the latch will be "optimized out" and so does not // appear in the technology schematic. always @( sel or a or b or c or d ) case( 1 ) sel==0: x = a; sel==1: x = b; sel==2: x = c; sel==3: x = d; endcase endmodule // case1