cd /home/faculty1/koppel/teach/v00/ex/syn1/
diff -c /home/faculty1/koppel/teach/v00/ex/syn1/latch.v\~ /home/faculty1/koppel/teach/v00/ex/syn1/latch.v
*** /home/faculty1/koppel/teach/v00/ex/syn1/latch.v~	Fri Apr 14 09:10:01 2000
--- /home/faculty1/koppel/teach/v00/ex/syn1/latch.v	Tue Apr 18 14:03:22 2000
***************
*** 113,121 ****
  
  // Form 2: Edge Triggered
  
! //    Describes registers clocked on the edge of a single signal.
! //    Registers can also be written with constants at asynchronous trigger.
! //
  
  // Basic Form
  
--- 113,121 ----
  
  // Form 2: Edge Triggered
  
! //    Describes registers clocked on the edge of a single signal which
! //    can also be written with a constant at an asynchronous trigger.
! 
  
  // Basic Form
  
***************
*** 154,178 ****
  //   code. (Whose value is known anyway.)
  //
  //   Assignments in <non-timing-statements> can assign any valid
! //   expression.  Timing controls cannot be used in
! //   <non-timing-statements>, nor can loops with a non-constant number
! //   of iterations.
  //
  // Inference of Registers (Synthesis of assignment statements.)
  //
  //    Registers synthesized for all assignments.
  //
  //    Unconditional assignment in <non-timing-statements>:
! //       Edge-triggered (on clock) load.
  //       x1 = a1 | a2; // x1 loaded with a1 | a2 on edge of clock.
  //
  //    Conditional assignment in <non-timing-statements>:
! //       Edge-triggered (on clock) load with enable signal.
  //       if( a3 ) x2 = a1 | a2; // x2 loaded with a1 | a2 on edge of clock if a3.
  //
  //    Assignments in <constant-assignments>
  //       Asynchronous set or reset triggered on signal in if condition.
  //       x1 = 0; // Load x1 with zero when sx true or false.
  //
  // Example:
  
--- 154,185 ----
  //   code. (Whose value is known anyway.)
  //
  //   Assignments in <non-timing-statements> can assign any valid
! //   expression.  That is, a signal can be used in an expression
! //   whether or not it appears in the event expression.  Timing
! //   controls cannot be used in <non-timing-statements>, nor can loops
! //   with a non-constant number of iterations.
  //
  // Inference of Registers (Synthesis of assignment statements.)
  //
  //    Registers synthesized for all assignments.
  //
  //    Unconditional assignment in <non-timing-statements>:
! //       Edge-triggered (on clock).
  //       x1 = a1 | a2; // x1 loaded with a1 | a2 on edge of clock.
  //
  //    Conditional assignment in <non-timing-statements>:
! //       Edge-triggered (on clock) with enable signal.
  //       if( a3 ) x2 = a1 | a2; // x2 loaded with a1 | a2 on edge of clock if a3.
  //
  //    Assignments in <constant-assignments>
  //       Asynchronous set or reset triggered on signal in if condition.
  //       x1 = 0; // Load x1 with zero when sx true or false.
+ //
+ //    Note: The same register CAN be written in <constant-assignments> and
+ //    <non-timing-statements>, see "a" below:  On a positive edge of
+ //    the clock (which may be sn) "a" will be loaded with "c". Whenever
+ //    "s1" is 1 a will be set to zero, when "s1" and "s2" are 0 "a"
+ //    will be set to one.
  //
  // Example:
  

Diff finished at Tue Apr 18 14:04:22