/// Sample code for LSU EE 4702-1 Spring 2001. // // Binary Full Adders // // Includes explicit structural, implicit structural, and // behavioral binary full adder descriptions, and a testbench. //////////////////////////////////////////////////////////////////////////////// // // A module containing three binary full adders, each described // a different way. // module bfas(ssum, scout, isum, icout, bsum, bcout, a, b, c); output ssum, scout, isum, icout, bsum, bcout; input a, b, c; bfa_structural str(ssum,scout,a,b,c); bfa_implicit impl(isum,icout,a,b,c); bfa_behavioral behav(bsum,bcout,a,b,c); endmodule // // Binary Full Adder Explicit Structural Description // module bfa_structural(sum,cout,a,b,c); input a,b,c; output sum,cout; wire term001, term010, term100,term111; wire ab, bc, ac; wire na, nb, nc; or o1(sum,term001,term010,term100,term111); or o2(cout,ab,bc,ac); and a1(term001,na,nb,c); and a2(term010,na,b,nc); and a3(term100,a,nb,nc); and a4(term111,a,b,c); not n1(na,a); not n2(nb,b); not n3(nc,c); and a10(ab,a,b); and a11(bc,b,c); and a12(ac,a,c); endmodule // Binary Full Adder Implicit Structural Description module bfa_implicit(sum,cout,a,b,c); input a,b,c; output sum,cout; assign sum = ~a & ~b & c | ~a & b & ~c | a & ~b & ~c | a & b & c; assign cout = a & b | b & c | a & c; endmodule // // Binary Full Adder Behavioral Description // // Uses Verilog that will be covered later in the course. module bfa_behavioral(sum,cout,a,b,c); input a,b,c; output sum,cout; reg sum,cout; // Covered soon: 2-bit register. reg [1:0] wholesum; // Covered later: execute begin/end block whenever a or b or c changes. always @( a or b or c ) begin wholesum = a + b + c; sum = wholesum[0]; cout = wholesum[1]; end endmodule // Covered later: tell synthesis program to ignore the code below (the // testbench). // exemplar translate_off // // Testbench // module testbfa(); integer realsum; integer abc; wire a = abc[2]; wire b = abc[1]; wire c = abc[0]; wire bfsum,bfcarry; bfa_behavioral fa(bfsum,bfcarry,a,b,c); initial begin for(abc=0; abc<8; abc=abc+1) begin #1; realsum = a + b + c; #1; if( realsum[0] != bfsum || realsum[1] != bfcarry ) $display("Error in %d + %d + %d = %d %d\n", a,b,c,bfcarry,bfsum); end $display("Finished testing.\n"); $stop; end endmodule