/// Generic ALU // To be included from l070.v. module `ALUNAME(result,op,a,b); input op, a, b; output result; reg [`WIDTH-1:0] result; wire [`WIDTH-1:0] a, b; wire op; always @( op or a or b ) case( op ) 0 : begin `OP0(result,a,b) end 1 : begin `OP1(result,a,b) end endcase endmodule