/// Final Exam Review

 /// Exam:  Wednesday, 9 May 7:30-9:30 (AM)
 //  Closed book, open everything else.
 //  No computers, no communication devices.

/// Topics

 /// EDA Overview

 // What is an HDL?
 // Design flow steps.

 /// Module Basics

 /// Variables and Data Types

 /// Operators

 /// Conditional and Looping Constructs

 /// Gates v. Modules

 /// Procedural Delays and Event Expressions

 /// Simulator Event Queue

 /// Functions and Tasks

 /// Synthesis Steps

 /// Synthesizable Forms (Leonardo)