// Sample code for LSU EE 4702-1 Spring 2001 // First example of Verilog code, xor and testbench. // // xor gate, structural description. // module myxor(x, a, b); input a, b; output x; wire an, bn, anb, abn; not n1(an, a); not n2(bn, b); and a1(anb, an, b); and a2(abn, a, bn); or o1(x, anb, abn); endmodule // myxor // exemplar translate_off // // Testbench for xor gate. // module testxor(); integer i; wire x; wire a = i[0]; wire b = i[1]; myxor x1(x, a, b); initial begin for(i=0; i<=3; i=i+1) begin #1; if( x !== a ^ b ) begin $display("Unexpected output."); $stop; end end $display("Passed test."); $stop; end endmodule // testxor