Information on the lectures given in class are listed below,
divided into roughly one-week sets. Information includes
when the lectures where given, and where applicable,
links to slides used in class. When possible
material will be added before it is used in class.
If material is not yet available see
lectures from last year.
Zoom Recording of Aug 25, 2021 LectureVariations on the design of a logical right shifter. Quick demonstration of Verilog simulation using Cadence Xcelium xrun and synthesis using Cadence Genus.
Zoom Recording of Aug 27, 2021 LectureQuick look at OSU standard cells. Quick demo of synthesis with timing constraints. Look at area and power of three synthesized shifter variations (operator,mux,logarithmic) and discussion of how they might differ from our expectations.
Verilog Review Covered 27 Aug, 8, 10 September 2021
Additional Material
Zoom Recording of Sep 8, 2021 Lecture[Starts with bad audio, fixed after a few minutes.] Specifying connections in module headers. The difference between parameters and ports.
Basic Simulation Covered 10, 13 September 2021
Additional Material
Zoom Recording of Sep 10, 2021 LectureModule instantiation tree and hierarchical names. Simulation terminology, including processes, sensitivity lists, and the event queue. Start of an example of how scheduling queue operates.
Zoom Recording of Sep 20, 2021 LectureSolution to 2018 Homework 1 (sorting modules sort2 and sort4). Beginning of l020-types, in which the difference between a net kind and a variable kind was explained.
Zoom Recording of Sep 24, 2021 LectureFinished l020-types: working with floating-point; associative and dynamic arrays. Started sample problem from 2018 Homework 3
Zoom Recording of Oct 1, 2021 LectureUsing generate statement to describe modules recursively. Recursive described sum (simple_tree) and minimum (min_t) modules.
Zoom Recording of Oct 15, 2021 LectureAs an example of how to apply the simple model, partly solved 2016 Final Exam Problem 2. Started l045, synthesis of behavioral code describing combinational logic. Covered simple statements and if/else statements.
Zoom Recording of Oct 15, 2021 LectureAs an example of how to apply the simple model, partly solved 2016 Final Exam Problem 2. Started l045, synthesis of behavioral code describing combinational logic. Covered simple statements and if/else statements.
Zoom Recording of Oct 20, 2021 LectureFinished l045, including the idx_min module. Described non-blocking assignments, drawing on material from Set 010 (l010-basic-behav.v) and the event queue material.
Zoom Recording of Nov 1, 2021 LectureSolution to Midterm Exam Problems 5-6. Inferencing of medium complexity arbitrary sequential logic descriptions. Inferencing of two variations on a multiply/accumulate module.
Zoom Recording of Oct 29, 2021 LectureSequential logic (from slides). How registers are inferred. Basic examples for individual registers, a simple count-up timer. For the count-up timer looked at variations to reduce critical path and change behavior. Example of module with multiple registers and combinational logic.
Zoom Recording of Nov 1, 2021 LectureSolution to Midterm Exam Problems 5-6. Inferencing of medium complexity arbitrary sequential logic descriptions. Inferencing of two variations on a multiply/accumulate module.
Zoom Recording of Nov 3, 2021 LectureDesign of a sequential shifter. Started with an overview and a lower-bound cost estimate. By end of class had code completed, but non-functional.
Zoom Recording of Nov 22, 2021 Lecture2021 Homework 5 solution (based on 2020 Final Exam Problems 1 and 3). Started cam (content-addressable memory) modules.
Zoom Recording of Nov 29, 2021 LectureHashed and sequential hashed versions of cam module. Use of a cam to implement a TLB (memory system component that translates virtual pages to physical pages.