EE 47XX - What's New

12 May 2000, 18:00:07 CDT
COURSE GRADES READY Sit down, make sure no one is looking, and click here. Have a good summer!

12 May 2000, 16:15:58 CDT
Grading update: Homework 6 graded. Check your class account E-mail. Course grades should be available within a few hours, or possibly later.

11 May 2000, 20:03:25 CDT
Grading update: Homework 5 graded. Check your class account E-mail. Course grades should be ready by tomorrow evening.

10 May 2000, 17:12:43 CDT
Linked final exam solution and related Verilog code to assignments and exams.

10 May 2000, 16:14:13 CDT
Final exam grades ready.. The average is 57.4 ... steady your hand and click here. Stop by to see your exam and a solution. The remaining homework and course grades may be available by the end of the week. Grading updates and a partial exam solution will be posted.

9 May 2000, 19:17:59 CDT
Grading update: Final exam grades may be available by tomorrow evening. Couse grades may be done by the end of the week.

8 May 2000, 12:27:04 CDT
Replaced gag final exam with the real thing.. Grades and a solution will be posted by the end of the week, grading status updates will be posted. Stop by to see a hand-written solution.

7 May 2000, 21:00:47 CDT
Make sure your alarm clock works and is set. Good luck tomorrow!

6 May 2000, 16:53:41 CDT
Linked additional sample final questions to assignments and exams page.

6 May 2000, 13:25:30 CDT
Additional practice problems may be posted over the weekend. The expiration timers for the whats new and course home page have been set to 30 minutes. (If you re-visit those pages in less than 30 minutes you'll have to click re-load.)

5 May 2000, 11:05:37 CDT
Linked sample final questions to assignments and exams page. These include additional questions not used in class. Also linked prefix code to lectures page. The Verilog descriptions of prefix trees is something I would have liked to cover, but there was no time, but they are being posted anyway.

4 May 2000, 19:05:47 CDT
Homework 4 graded. Check your class account E-mail.

3 May 2000, 14:59:23 CDT
Linked solution to hw 6 to assignments and exams page. Don't forget, the final exam is the Monday, the first day of finals, at 7:30 (am) (yes, am) CDT.

2 May 2000, 12:18:38 CDT
Extended deadline extended to 17:00 (5pm) CDT Tuesday, 2 May.

1 May 2000, 10:59:45 CDT
Added question on doing something like this word[pos+7:pos] = byte to the FAQ page.

1 May 2000, 9:45:56 CDT
Deadline for HW 6 extended to Tuesday 2 May, 14:00. [See 2 May entry.]

28 April 2000, 17:58:16 CDT
Modified testbench in hw 6 template. The new testbench starts with easy tests, then does intermediate, then hard. In the easy tests inclk and outclk don't overlap. In the intermediate tests there will never simultaneously be a positive edge on inclk and outclk. The hard tests are the same as the previous testbench. A parameter "stop_on_err" has been added to the testbench. If that's 1 the testbench stops two cycles after it encounters an error (for your debugging convenience). If stop_on_err is zero execution will continue and a tally of errors will be printed. Also, if tests are passed instead of printing "Done with tests" it prints a message with a level of enthusiasm appropriate to the accomplishment.

28 April 2000, 16:53:03 CDT
For a hint on homework 6 see the fifo code covered in March. A modified hw 6 testbench will be posted soon; the modified testbench will start with easier tests and finish with the tests currently given. A synthesized module that passes the easier tests will be eligible for partial credit.

28 April 2000, 10:47:08 CDT
Linked linear search associative memory (using both implicit and explicit finite state machines) and their testbench to lectures page.

27 April 2000, 17:19:13 CDT
Added question on getting word[pos+3:pos] to work to FAQ page.

27 April 2000, 15:43:46 CDT
Linked solution to homework 5 to assignments and exams page.

26 April 2000, 13:01:32 CDT
Deadline for homework 6 extended to Monday, 1 May 2000 about 14:30.

19 April 2000, 8:23:18 CDT
Homework 6 assigned, due Friday, 28 April 2000. [See entry above.] Solution template available.

18 April 2000, 14:06:21 CDT
Made minor changes to latch.v (the three forms, notes on the synthesis of Verilog code) which may help in solving homework 5. To see the changes (as reported by diff) click here.

17 April 2000, 16:49:13 CDT
Added instructions on how to synthesize and compile using Emacs to the FAQ page (added to answer posted earlier).

17 April 2000, 11:03:24 CDT
Added a question on simulating synthesized code to the FAQ page.

13 April 2000, 13:19:32 CDT
Linked Verilog code and important notes on synthesis of procedural code (latches, etc.) to the lectures page. Recommended for solving the homework.

12 April 2000, 18:47:35 CDT
Linked manuals for the synthesis program to references page. Code examples of synthesizing latches will be posted tomorrow.

12 April 2000, 11:30:56 CDT
Linked code on case statements covered on Monday and Wednesday to lectures page. Code on synthesizing latches, helpful in solving the homework, will be added later.

12 April 2000, 8:11:32 CDT
Homework 5 assigned, due Wednesday, 19 April 2000.

9 April 2000, 16:09:53 CDT
Homework 3 graded; check your E-mail.

8 April 2000, 13:07:04 CDT
Added link to Dr. Ramunujam's Fall 2000 undergraduate synthesis course.

6 April 2000, 18:56:25 CDT
Linked midterm exam solution and related Verilog code to the assignments and exams page.

6 April 2000, 17:50:11 CDT
Midterm exam grades ready The average is 56.4, the range is 22-83. Prepare yourself and click here.

5 April 2000, 17:32:10 CDT
Midterm exam grades should be available some time tomorrow.

5 April 2000, 9:55:57 CDT
Linked midterm exam to assignments and exams page. A solution and an estimated completion time for grading will be posted later.

4 April 2000, 9:16:57 CDT
The exam is closed book but a note sheet is allowed, see the new FAQ entry. (In part, the exam is closed book because the book is expensive.)

3 April 2000, 18:15:30 CDT
Linked solution to practice midterm and related Verilog code to assignments and exams page.

30 March 2000, 17:04:21 CST
Linked practice midterm to assignments and exams page.

24 March 2000, 15:34:52 CST
Linked homework 4 solution to assignments and exams page.

21 March 2000, 16:52:28 CST
Homework 2 graded, check your E-mail for the graded assignment. Those submitting paper-only solutions can pick them up in my office.

17 March 2000, 10:08:16 CST
Changed midterm exam time: Exam will now be held the Wednesday after spring break, 5 April 2000.

Homework 4 will be copied a little after 14:30 today.

16 March 2000, 15:33:48 CST
Posted a possibly less-confusing hint for homework 4.

13 March 2000, 10:04:14 CST
Relaxed requirements on homework 4 and specified features needed in testbench. See the revised assignment and the hint given in class.

11 March 2000, 15:51:53 CST
Linked Verilog code illustrating tasks, functions, and memories, to the lectures page. Also updated code illustrating the case statements.

10 March 2000, 14:54:49 CST
Midterm Exam scheduled for Friday, 24 March 2000, during regular class time. [Midterm exam changed, see 17 March 2000 entry.]

10 March 2000, 12:44:22 CST
Linked homework 4 solution template to the assignments and exams page.

10 March 2000, 8:15:26 CST
Linked homework 4 to the assignments and exams page, due 17 March 2000. A solution template will be made available later today. Linked homework 3 solution to assignments and exams page.

2 March 2000, 9:36:52 CST
Added a question on computing rpx to the FAQ page.

29 February 2000, 12:16:32 CST
A new version, 5.3d, of ModelSim has been installed. The new version should fix problems with the Wave window crashing when the Next Event button was pressed. Let me know if there are any problems with ModelSim crashing.

28 February 2000, 18:41:43 CST
Added a question on the conditional operator ( foo ? bar : foobar ) to the FAQ page.

28 February 2000, 17:38:21 CST
Posted revised homework 3 and a solution template to the assignments and exams page. Due Friday, 3 March.

28 February 2000, 11:44:56 CST
Homework 3 has been shortened (actually, split) and the deadline has been extended to Friday, 3 March. Homework 3 now consists of problems 1 and 2, the remaining problems will be part of homework 4. Updated homework assignments reflecting these changes and testbench code for homework 3 will be posted later today.

26 February 2000, 14:53:29 CST
Linked examples of case statement to lectures page.

25 February 2000, 10:45:19 CST
Linked solution to hw 2 to assignments and exams page. Homework 1 has been graded and can be picked up.

22 February 2000, 19:04:42 CST
Added a question on debugging homework solution to the FAQ page.

Those who are generating their own clock signal, make sure it's not too high, 10 kHz should be fast enough. To see if it's fast enough compare it to pd. It's too fast if your simulation takes too long or you run out of disk space too soon.

22 February 2000, 15:08:37 CST
There is a minor problem in the testbench that will cause it to report zero errors when the output of the tachometer is undefined. A corrected testbench has been posted. If you prefer to edit the file you're working on, change all four occurrences of   16'bx    to   `bits'bx  .

22 February 2000, 12:31:23 CST
Added a question on the "Error: === operator invalid for REAL" message and on disappearing windows to the FAQ page.

22 February 2000, 11:08:26 CST
Added a why-doesn't-pd1-change question to the FAQ page.

22 February 2000, 10:04:06 CST
Modified the default .emacs file so that Emacs' background is white and Courier is used as the default font.

21 February 2000, 19:14:39 CST
Added references on Unix to references page.

21 February 2000, 18:24:59 CST
Added homework assignment submission instructions to procedures page. The instructions are voluntary for the first assignment, but they could hardly be easier so you might as well follow them.

21 February 2000, 13:18:31 CST
Added a "Should the simulation take a long time" question to the FAQ page.

20 February 2000, 14:52:46 CST
Added question about multiplication and division for homework 2, which is due Wednesday, 23 February, to FAQ page.

18 February 2000, 17:52:44 CST
Linked bean counter problem and Verilog solution to the lectures page.

18 February 2000, 15:49:34 CST
Added Where-do-I-telnet-into question to the FAQ page.

17 February 2000, 20:55:27 CST
Homework 2 and a solution template linked to assignments and exams page. Due Wednesday, 23 February. Homework 3 also linked to assignments and exams page, that's due 1 March.

16 February 2000, 19:05:48 CST
Homework 2 will be assigned tomorrow.

14 February 2000, 17:35:59 CST
Linked events example code used in Friday's class to lectures page.

14 February 2000, 16:37:32 CST
Added information about using your home computer to run graphical software to the FAQ and procedures pages. Also added questions on unsupported Verilog syntax to FAQ page.

11 February 2000, 16:24:40 CST
For hw1, problem 3, make sure your solution only contains structural code. Add delays only. See binary full adder for examples of the delay syntax you'll need in the solution. A question on this assignment was added to the FAQ page.

10 February 2000, 15:43:31 CST
Linked a FAQ page to course home page.

10 February 2000, 10:33:05 CST
Posted corrected code template for hw 1 problem 3. The original testbench for problem 3 did not produce the waveform illustrated in the homework assignment.

9 February 2000, 19:12:09 CST
Linked code samples used in class on Monday (delays, nonblocking assignments etc.), and code that would have been used on Wednesday morning if I could have logged in (reg/wire rules, assignment) to lectures page.

9 February 2000, 18:28:39 CST
Added a procedures page giving instructions on how to use the ModelSim software and the Emacs text editor.

4 February 2000, 18:40:07 CST
Linked counter code to lectures page. Also made minor changes to bfat.v, (binary full adders with timing).

4 February 2000, 10:16:46 CST
The computer accounts are ready! They'll be distributed in class on Monday but they can be picked up in my office before then.

3 February 2000, 20:10:12 CST
Added a references page which includes information on the simulator software and the Verilog language. See the entry on this page for the ModelSim EE/SE Tutorial for information on how to solve the homework (which still hasn't been officially assigned).

2 February 2000, 18:39:43 CST
Linked Set 2 slides and adder code to lectures page.

2 February 2000, 18:20:29 CST
Linked preview of homework to assignments and exams page. No due date yet.

21 January 2000, 16:42:31 CST
Linked binary full adder code to lectures page.

19 January 2000, 19:45:23 CST
Verilog for XOR gate linked to lectures page.

19 January 2000, 12:49:42 CST
Added lectures pages containing links to lecture notes used in class. Later today Verilog code samples used in class and other material will be added.

2 November 1999, 10:27:34 CST
Added prerequisite (credit or registration in EE 3750) to syllabus.

28 October 1999, 16:08:54 CDT
Web pages set up.