Office hours: MW 8:45 am - 10:25 am; F 10:30 am - 12:10 pm

Teaching Assistants: Fang Liu (office hours: 8:00-9:00 am) and Yao Xu.

Topics: Sequential logic design and analysis, latches and flip-flops, finite state machines, counters and registers, elements of digital sysem design

Text: Fundamentals of Digital Logic with Verilog Design, second edition, by Stephen Brown and Zvonko Vranesic, McGraw Hill, 2008.

Prerequisite: EE 2720

Basis for grading:

Phone: (225) 578-5238
Fax: (225) 578-5200
E-mail: